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Add FPMR register and update dependencies of FP8 instructions (#102910)
Currently FP8 instructions are missing dependecies on system registers, namely FPMR and FPCR. This patch fixes this issue.
1 parent 5d28678 commit ff90640

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7 files changed

+69
-18
lines changed

7 files changed

+69
-18
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10148,7 +10148,7 @@ let Predicates = [HasD128] in {
1014810148
// 2023 Architecture Extensions:
1014910149
//===----------------------------===//
1015010150

10151-
let Predicates = [HasFP8] in {
10151+
let Uses = [FPMR, FPCR], Predicates = [HasFP8] in {
1015210152
defm F1CVTL : SIMDMixedTwoVectorFP8<0b00, "f1cvtl">;
1015310153
defm F2CVTL : SIMDMixedTwoVectorFP8<0b01, "f2cvtl">;
1015410154
defm BF1CVTL : SIMDMixedTwoVectorFP8<0b10, "bf1cvtl">;
@@ -10173,7 +10173,7 @@ let Predicates = [HasNEON, HasFAMINMAX] in {
1017310173
}
1017410174
} // End let Predicates = [HasNEON, HasFAMINMAX]
1017510175

10176-
let Predicates = [HasFP8FMA] in {
10176+
let Uses = [FPMR, FPCR], Predicates = [HasFP8FMA] in {
1017710177
defm FMLALBlane : SIMDThreeSameVectorMLAIndex<0b0, "fmlalb">;
1017810178
defm FMLALTlane : SIMDThreeSameVectorMLAIndex<0b1, "fmlalt">;
1017910179
defm FMLALLBBlane : SIMDThreeSameVectorMLALIndex<0b0, 0b00, "fmlallbb">;
@@ -10189,12 +10189,12 @@ let Predicates = [HasFP8FMA] in {
1018910189
defm FMLALLTT : SIMDThreeSameVectorMLAL<0b1, 0b01, "fmlalltt">;
1019010190
} // End let Predicates = [HasFP8FMA]
1019110191

10192-
let Predicates = [HasFP8DOT2] in {
10192+
let Uses = [FPMR, FPCR], Predicates = [HasFP8DOT2] in {
1019310193
defm FDOTlane : SIMDThreeSameVectorFP8DOT2Index<"fdot">;
1019410194
defm FDOT : SIMDThreeSameVectorDOT2<"fdot">;
1019510195
} // End let Predicates = [HasFP8DOT2]
1019610196

10197-
let Predicates = [HasFP8DOT4] in {
10197+
let Uses = [FPMR, FPCR], Predicates = [HasFP8DOT4] in {
1019810198
defm FDOTlane : SIMDThreeSameVectorFP8DOT4Index<"fdot">;
1019910199
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
1020010200
} // End let Predicates = [HasFP8DOT4]

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -479,6 +479,7 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
479479
}
480480

481481
markSuperRegs(Reserved, AArch64::FPCR);
482+
markSuperRegs(Reserved, AArch64::FPMR);
482483
markSuperRegs(Reserved, AArch64::FPSR);
483484

484485
if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,9 @@ def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
147147
// Floating-point control register
148148
def FPCR : AArch64Reg<0, "fpcr">;
149149

150+
// Floating-point Mode Register
151+
def FPMR : AArch64Reg<0, "fpmr">;
152+
150153
// Floating-point status register.
151154
def FPSR : AArch64Reg<0, "fpsr">;
152155

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4244,19 +4244,18 @@ def FMLALLTT_ZZZ : sve2_fp8_mla<0b011, ZPR32, "fmlalltt">;
42444244

42454245
let Predicates = [HasSSVE_FP8DOT2] in {
42464246
// FP8 Widening Dot-Product - Indexed Group
4247-
defm FDOT_ZZZI_BtoH : sve2_fp8_dot_indexed<"fdot">;
4247+
defm FDOT_ZZZI_BtoH : sve2_fp8_dot_indexed_h<"fdot">;
42484248
// FP8 Widening Dot-Product - Group
42494249
// TODO: Replace nxv16i8 by nxv16f8
4250-
defm FDOT_ZZZ_BtoH : sve_float_dot<0b0, 0b1, ZPR16, ZPR8, "fdot", nxv16i8, null_frag>;
4250+
defm FDOT_ZZZ_BtoH : sve_fp8_dot<0b0, ZPR16, "fdot">;
42514251
}
42524252

42534253
// TODO: Replace nxv16i8 by nxv16f8
42544254
let Predicates = [HasSSVE_FP8DOT4] in {
42554255
// FP8 Widening Dot-Product - Indexed Group
4256-
defm FDOT_ZZZI_BtoS : sve_float_dot_indexed<0b1, 0b01, ZPR8, ZPR3b8, "fdot",
4257-
nxv16i8, null_frag>;
4256+
defm FDOT_ZZZI_BtoS : sve2_fp8_dot_indexed_s<"fdot">;
42584257
// FP8 Widening Dot-Product - Group
4259-
defm FDOT_ZZZ_BtoS : sve_float_dot<0b1, 0b1, ZPR32, ZPR8, "fdot", nxv16i8, null_frag>;
4258+
defm FDOT_ZZZ_BtoS : sve_fp8_dot<0b1, ZPR32, "fdot">;
42604259
}
42614260

42624261
let Predicates = [HasSVE2orSME2, HasLUT] in {

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2240,7 +2240,9 @@ multiclass sme2_cvt_vg2_single<string mnemonic, bits<5> op, ValueType out_vt,
22402240

22412241
// SME2 multi-vec FP8 down convert two registers
22422242
multiclass sme2_fp8_cvt_vg2_single<string mnemonic, bit op> {
2243-
def NAME : sme2_cvt_vg2_single<mnemonic, {op, 0b1000}, ZPR8, ZZ_h_mul_r>;
2243+
def NAME : sme2_cvt_vg2_single<mnemonic, {op, 0b1000}, ZPR8, ZZ_h_mul_r>{
2244+
let Uses = [FPMR, FPCR];
2245+
}
22442246
}
22452247

22462248
class sme2_cvt_unpk_vector_vg2<bits<2>sz, bits<3> op, bit u, RegisterOperand first_ty,
@@ -2273,7 +2275,9 @@ multiclass sme2p1_fp_cvt_vector_vg2_single<string mnemonic, bit l> {
22732275

22742276
// SME2 multi-vec FP8 up convert two registers
22752277
multiclass sme2p1_fp8_cvt_vector_vg2_single<string mnemonic, bits<2> opc, bit L> {
2276-
def _NAME : sme2_cvt_unpk_vector_vg2<opc, 0b110, L, ZZ_h_mul_r, ZPR8, mnemonic>;
2278+
def _NAME : sme2_cvt_unpk_vector_vg2<opc, 0b110, L, ZZ_h_mul_r, ZPR8, mnemonic>{
2279+
let Uses = [FPMR, FPCR];
2280+
}
22772281
}
22782282

22792283

@@ -2536,6 +2540,7 @@ class sme2_fp8_multi_vec_array_vg4_index<string mnemonic, bit T>
25362540
let Inst{10} = i{1};
25372541
let Inst{3} = i{0};
25382542
let AsmString = !strconcat(mnemonic, "{\t$ZAda[$Rv, $imm3, vgx4], $Zn, $Zm$i}");
2543+
let Uses = [FPMR, FPCR];
25392544
}
25402545

25412546
// SME2 multi-vec ternary indexed two registers 64-bit

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 47 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8708,6 +8708,12 @@ multiclass sve_float_dot<bit bf, bit o2, ZPRRegOp dst_ty, ZPRRegOp src_ty,
87088708
def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, InVT, InVT, !cast<Instruction>(NAME)>;
87098709
}
87108710

8711+
multiclass sve_fp8_dot<bit bf, ZPRRegOp dst_ty, string asm> {
8712+
def NAME : sve_float_dot<bf, 0b1, dst_ty, ZPR8, asm>{
8713+
let Uses = [FPMR, FPCR];
8714+
}
8715+
}
8716+
87118717
class sve_float_dot_indexed<bit bf, ZPRRegOp dst_ty, ZPRRegOp src1_ty,
87128718
ZPRRegOp src2_ty, Operand iop_ty, string asm>
87138719
: I<(outs dst_ty:$Zda), (ins dst_ty:$_Zda, src1_ty:$Zn, src2_ty:$Zm, iop_ty:$iop),
@@ -10212,6 +10218,7 @@ class sve2_fp8_cvt_single<bit L, bits<2> opc, string mnemonic,
1021210218
let Inst{11-10} = opc;
1021310219
let Inst{9-5} = Zn;
1021410220
let Inst{4-0} = Zd;
10221+
let Uses = [FPMR, FPCR];
1021510222
}
1021610223

1021710224
multiclass sve2_fp8_cvt_single<bit L, bits<2> opc, string mnemonic> {
@@ -10231,6 +10238,7 @@ class sve2_fp8_down_cvt_single<bits<2> opc, string mnemonic,
1023110238
let Inst{9-6} = Zn;
1023210239
let Inst{5} = 0b0;
1023310240
let Inst{4-0} = Zd;
10241+
let Uses = [FPMR, FPCR];
1023410242
}
1023510243

1023610244
multiclass sve2_fp8_down_cvt_single<bits<2> opc, string mnemonic, RegisterOperand src> {
@@ -10259,6 +10267,7 @@ class sve2_fp8_mla_long_by_indexed_elem<bit T, string mnemonic>
1025910267
let Constraints = "$Zda = $_Zda";
1026010268
let DestructiveInstType = DestructiveOther;
1026110269
let ElementSize = ZPR16.ElementSize;
10270+
let Uses = [FPMR, FPCR];
1026210271
}
1026310272

1026410273
// FP8 Widening Multiply-Add (Long)/(Long Long) Group
@@ -10282,6 +10291,7 @@ class sve2_fp8_mla<bits<3>opc, ZPRRegOp dst_ty, string mnemonic>
1028210291
let Constraints = "$Zda = $_Zda";
1028310292
let DestructiveInstType = DestructiveOther;
1028410293
let ElementSize = dst_ty.ElementSize;
10294+
let Uses = [FPMR, FPCR];
1028510295
}
1028610296

1028710297
// FP8 Widening Multiply-Add Long Long - Indexed Group
@@ -10306,15 +10316,48 @@ class sve2_fp8_mla_long_long_by_indexed_elem<bits<2> TT, string mnemonic>
1030610316
let Constraints = "$Zda = $_Zda";
1030710317
let DestructiveInstType = DestructiveOther;
1030810318
let ElementSize = ZPR32.ElementSize;
10319+
let Uses = [FPMR, FPCR];
10320+
}
10321+
10322+
class sve_fp8_dot_indexed<bits<4> opc, ZPRRegOp dst_ty, Operand iop_ty, string mnemonic>
10323+
: I<(outs dst_ty:$Zda), (ins dst_ty:$_Zda, ZPR8:$Zn, ZPR3b8:$Zm, iop_ty:$iop),
10324+
mnemonic, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
10325+
bits<5> Zda;
10326+
bits<5> Zn;
10327+
bits<3> Zm;
10328+
let Inst{31-23} = 0b011001000;
10329+
let Inst{22} = opc{3};
10330+
let Inst{21} = 0b1;
10331+
let Inst{20-19} = opc{2-1};
10332+
let Inst{18-16} = Zm;
10333+
let Inst{15-12} = 0b0100;
10334+
let Inst{11} = opc{0};
10335+
let Inst{10} = 0b1;
10336+
let Inst{9-5} = Zn;
10337+
let Inst{4-0} = Zda;
10338+
10339+
let Uses = [FPMR, FPCR];
10340+
let Constraints = "$Zda = $_Zda";
10341+
let DestructiveInstType = DestructiveOther;
10342+
let hasSideEffects = 0;
10343+
let mayRaiseFPException = 1;
1030910344
}
1031010345

1031110346
// FP8 Widening Dot-Product - Indexed Group
10312-
multiclass sve2_fp8_dot_indexed<string mnemonic>{
10313-
def NAME : sve_float_dot_indexed<0b0, ZPR16, ZPR8, ZPR3b8, VectorIndexH, mnemonic> {
10347+
multiclass sve2_fp8_dot_indexed_h<string asm>{
10348+
def NAME : sve_fp8_dot_indexed<{0, ?, ?, ?}, ZPR16, VectorIndexH, asm> {
1031410349
bits<3> iop;
10350+
1031510351
let Inst{20-19} = iop{2-1};
10316-
let Inst{11} = iop{0};
10317-
let Inst{10} = 0b1;
10352+
let Inst{11} = iop{0};
10353+
}
10354+
}
10355+
10356+
multiclass sve2_fp8_dot_indexed_s<string asm>{
10357+
def NAME : sve_fp8_dot_indexed<{1, ?, ?, 0}, ZPR32, VectorIndexS32b, asm> {
10358+
bits<2> iop;
10359+
10360+
let Inst{20-19} = iop{1-0};
1031810361
}
1031910362
}
1032010363

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