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[X86] LowerBITREVERSE - support SSE-only GFNI i32/i64 bitreverse
Support Tremont CPUs which don't have AVX but do have GFNI. Noticed while trying to workout how to clean up the costmodel for GFNI bitreverse
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2 files changed

+15
-48
lines changed

2 files changed

+15
-48
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1286,6 +1286,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
12861286
setOperationAction(ISD::CTLZ, VT, Custom);
12871287
}
12881288

1289+
if (Subtarget.hasGFNI()) {
1290+
setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
1291+
setOperationAction(ISD::BITREVERSE, MVT::i64, Custom);
1292+
}
1293+
12891294
// These might be better off as horizontal vector ops.
12901295
setOperationAction(ISD::ADD, MVT::i16, Custom);
12911296
setOperationAction(ISD::ADD, MVT::i32, Custom);
@@ -1496,11 +1501,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14961501
setOperationAction(ISD::TRUNCATE, MVT::v32i32, Custom);
14971502
setOperationAction(ISD::TRUNCATE, MVT::v32i64, Custom);
14981503

1499-
if (Subtarget.hasGFNI()) {
1500-
setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
1501-
setOperationAction(ISD::BITREVERSE, MVT::i64, Custom);
1502-
}
1503-
15041504
for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
15051505
setOperationAction(ISD::SETCC, VT, Custom);
15061506
setOperationAction(ISD::CTPOP, VT, Custom);
@@ -31337,12 +31337,9 @@ static SDValue LowerBITREVERSE(SDValue Op, const X86Subtarget &Subtarget,
3133731337
if (VT.is256BitVector() && !Subtarget.hasInt256())
3133831338
return splitVectorIntUnary(Op, DAG, DL);
3133931339

31340-
// Lower i32/i64 to GFNI as vXi8 BITREVERSE + BSWAP
31340+
// Lower i32/i64 as vXi8 BITREVERSE + BSWAP
3134131341
if (!VT.isVector()) {
31342-
31343-
assert((VT.getScalarType() == MVT::i32) ||
31344-
(VT.getScalarType() == MVT::i64));
31345-
31342+
assert((VT == MVT::i32 || VT == MVT::i64) && "Only tested for i32/i64");
3134631343
MVT VecVT = MVT::getVectorVT(VT, 128 / VT.getSizeInBits());
3134731344
SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In);
3134831345
Res = DAG.getNode(ISD::BITREVERSE, DL, MVT::v16i8,

llvm/test/CodeGen/X86/vector-bitreverse.ll

Lines changed: 8 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -254,24 +254,10 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
254254
;
255255
; GFNISSE-LABEL: test_bitreverse_i32:
256256
; GFNISSE: # %bb.0:
257-
; GFNISSE-NEXT: # kill: def $edi killed $edi def $rdi
258-
; GFNISSE-NEXT: bswapl %edi
259-
; GFNISSE-NEXT: movl %edi, %eax
260-
; GFNISSE-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F
261-
; GFNISSE-NEXT: shll $4, %eax
262-
; GFNISSE-NEXT: shrl $4, %edi
263-
; GFNISSE-NEXT: andl $252645135, %edi # imm = 0xF0F0F0F
264-
; GFNISSE-NEXT: orl %eax, %edi
265-
; GFNISSE-NEXT: movl %edi, %eax
266-
; GFNISSE-NEXT: andl $858993459, %eax # imm = 0x33333333
267-
; GFNISSE-NEXT: shrl $2, %edi
268-
; GFNISSE-NEXT: andl $858993459, %edi # imm = 0x33333333
269-
; GFNISSE-NEXT: leal (%rdi,%rax,4), %eax
270-
; GFNISSE-NEXT: movl %eax, %ecx
271-
; GFNISSE-NEXT: andl $1431655765, %ecx # imm = 0x55555555
272-
; GFNISSE-NEXT: shrl %eax
273-
; GFNISSE-NEXT: andl $1431655765, %eax # imm = 0x55555555
274-
; GFNISSE-NEXT: leal (%rax,%rcx,2), %eax
257+
; GFNISSE-NEXT: movd %edi, %xmm0
258+
; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
259+
; GFNISSE-NEXT: movd %xmm0, %eax
260+
; GFNISSE-NEXT: bswapl %eax
275261
; GFNISSE-NEXT: retq
276262
;
277263
; GFNIAVX-LABEL: test_bitreverse_i32:
@@ -343,26 +329,10 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
343329
;
344330
; GFNISSE-LABEL: test_bitreverse_i64:
345331
; GFNISSE: # %bb.0:
346-
; GFNISSE-NEXT: bswapq %rdi
347-
; GFNISSE-NEXT: movq %rdi, %rax
348-
; GFNISSE-NEXT: shrq $4, %rax
349-
; GFNISSE-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F
350-
; GFNISSE-NEXT: andq %rcx, %rax
351-
; GFNISSE-NEXT: andq %rcx, %rdi
352-
; GFNISSE-NEXT: shlq $4, %rdi
353-
; GFNISSE-NEXT: orq %rax, %rdi
354-
; GFNISSE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
355-
; GFNISSE-NEXT: movq %rdi, %rcx
356-
; GFNISSE-NEXT: andq %rax, %rcx
357-
; GFNISSE-NEXT: shrq $2, %rdi
358-
; GFNISSE-NEXT: andq %rax, %rdi
359-
; GFNISSE-NEXT: leaq (%rdi,%rcx,4), %rax
360-
; GFNISSE-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
361-
; GFNISSE-NEXT: movq %rax, %rdx
362-
; GFNISSE-NEXT: andq %rcx, %rdx
363-
; GFNISSE-NEXT: shrq %rax
364-
; GFNISSE-NEXT: andq %rcx, %rax
365-
; GFNISSE-NEXT: leaq (%rax,%rdx,2), %rax
332+
; GFNISSE-NEXT: movq %rdi, %xmm0
333+
; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
334+
; GFNISSE-NEXT: movq %xmm0, %rax
335+
; GFNISSE-NEXT: bswapq %rax
366336
; GFNISSE-NEXT: retq
367337
;
368338
; GFNIAVX-LABEL: test_bitreverse_i64:

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