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Mel-ChenMel-Chen
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[LV] Add test cases for reverse accesses involving irregular types. nfc (#135139)
Add a test with irregular type to ensure the vector load/store instructions are not generated.
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‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll

Lines changed: 242 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -429,7 +429,249 @@ exit:
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ret void
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}
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432+
define void @vector_reverse_irregular_type(ptr noalias %A, ptr noalias %B) {
433+
; RV64-LABEL: define void @vector_reverse_irregular_type(
434+
; RV64-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {
435+
; RV64-NEXT: [[ENTRY:.*]]:
436+
; RV64-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
437+
; RV64: [[VECTOR_PH]]:
438+
; RV64-NEXT: br label %[[VECTOR_BODY:.*]]
439+
; RV64: [[VECTOR_BODY]]:
440+
; RV64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
441+
; RV64-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]
442+
; RV64-NEXT: [[DEC_IV:%.*]] = add i64 [[OFFSET_IDX]], 0
443+
; RV64-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], -1
444+
; RV64-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], -2
445+
; RV64-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], -3
446+
; RV64-NEXT: [[IV_NEXT:%.*]] = add nsw i64 [[DEC_IV]], -1
447+
; RV64-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP1]], -1
448+
; RV64-NEXT: [[TMP6:%.*]] = add nsw i64 [[TMP2]], -1
449+
; RV64-NEXT: [[TMP7:%.*]] = add nsw i64 [[TMP3]], -1
450+
; RV64-NEXT: [[ARRAYIDX_B:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[IV_NEXT]]
451+
; RV64-NEXT: [[TMP9:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP5]]
452+
; RV64-NEXT: [[TMP10:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP6]]
453+
; RV64-NEXT: [[TMP11:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP7]]
454+
; RV64-NEXT: [[TMP0:%.*]] = load i7, ptr [[ARRAYIDX_B]], align 1
455+
; RV64-NEXT: [[TMP13:%.*]] = load i7, ptr [[TMP9]], align 1
456+
; RV64-NEXT: [[TMP14:%.*]] = load i7, ptr [[TMP10]], align 1
457+
; RV64-NEXT: [[TMP15:%.*]] = load i7, ptr [[TMP11]], align 1
458+
; RV64-NEXT: [[TMP16:%.*]] = insertelement <4 x i7> poison, i7 [[TMP0]], i32 0
459+
; RV64-NEXT: [[TMP17:%.*]] = insertelement <4 x i7> [[TMP16]], i7 [[TMP13]], i32 1
460+
; RV64-NEXT: [[TMP18:%.*]] = insertelement <4 x i7> [[TMP17]], i7 [[TMP14]], i32 2
461+
; RV64-NEXT: [[TMP19:%.*]] = insertelement <4 x i7> [[TMP18]], i7 [[TMP15]], i32 3
462+
; RV64-NEXT: [[TMP20:%.*]] = add <4 x i7> [[TMP19]], splat (i7 1)
463+
; RV64-NEXT: [[TMP21:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[IV_NEXT]]
464+
; RV64-NEXT: [[TMP22:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP5]]
465+
; RV64-NEXT: [[TMP23:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP6]]
466+
; RV64-NEXT: [[TMP24:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP7]]
467+
; RV64-NEXT: [[TMP25:%.*]] = extractelement <4 x i7> [[TMP20]], i32 0
468+
; RV64-NEXT: store i7 [[TMP25]], ptr [[TMP21]], align 1
469+
; RV64-NEXT: [[TMP26:%.*]] = extractelement <4 x i7> [[TMP20]], i32 1
470+
; RV64-NEXT: store i7 [[TMP26]], ptr [[TMP22]], align 1
471+
; RV64-NEXT: [[TMP27:%.*]] = extractelement <4 x i7> [[TMP20]], i32 2
472+
; RV64-NEXT: store i7 [[TMP27]], ptr [[TMP23]], align 1
473+
; RV64-NEXT: [[TMP28:%.*]] = extractelement <4 x i7> [[TMP20]], i32 3
474+
; RV64-NEXT: store i7 [[TMP28]], ptr [[TMP24]], align 1
475+
; RV64-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
476+
; RV64-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1020
477+
; RV64-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
478+
; RV64: [[MIDDLE_BLOCK]]:
479+
; RV64-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]]
480+
; RV64: [[SCALAR_PH]]:
481+
; RV64-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 3, %[[MIDDLE_BLOCK]] ], [ 1023, %[[ENTRY]] ]
482+
; RV64-NEXT: br label %[[FOR_BODY:.*]]
483+
; RV64: [[FOR_BODY]]:
484+
; RV64-NEXT: [[DEC_IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], %[[FOR_BODY]] ]
485+
; RV64-NEXT: [[IV_NEXT1]] = add nsw i64 [[DEC_IV1]], -1
486+
; RV64-NEXT: [[ARRAYIDX_B1:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[IV_NEXT1]]
487+
; RV64-NEXT: [[TMP30:%.*]] = load i7, ptr [[ARRAYIDX_B1]], align 1
488+
; RV64-NEXT: [[ADD:%.*]] = add i7 [[TMP30]], 1
489+
; RV64-NEXT: [[ARRAYIDX_A:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[IV_NEXT1]]
490+
; RV64-NEXT: store i7 [[ADD]], ptr [[ARRAYIDX_A]], align 1
491+
; RV64-NEXT: [[CMP:%.*]] = icmp ugt i64 [[DEC_IV1]], 1
492+
; RV64-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
493+
; RV64: [[EXIT]]:
494+
; RV64-NEXT: ret void
495+
;
496+
; RV32-LABEL: define void @vector_reverse_irregular_type(
497+
; RV32-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {
498+
; RV32-NEXT: [[ENTRY:.*]]:
499+
; RV32-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
500+
; RV32: [[VECTOR_PH]]:
501+
; RV32-NEXT: br label %[[VECTOR_BODY:.*]]
502+
; RV32: [[VECTOR_BODY]]:
503+
; RV32-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
504+
; RV32-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]
505+
; RV32-NEXT: [[DEC_IV:%.*]] = add i64 [[OFFSET_IDX]], 0
506+
; RV32-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], -1
507+
; RV32-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], -2
508+
; RV32-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], -3
509+
; RV32-NEXT: [[IV_NEXT:%.*]] = add nsw i64 [[DEC_IV]], -1
510+
; RV32-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP1]], -1
511+
; RV32-NEXT: [[TMP6:%.*]] = add nsw i64 [[TMP2]], -1
512+
; RV32-NEXT: [[TMP7:%.*]] = add nsw i64 [[TMP3]], -1
513+
; RV32-NEXT: [[ARRAYIDX_B:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[IV_NEXT]]
514+
; RV32-NEXT: [[TMP9:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP5]]
515+
; RV32-NEXT: [[TMP10:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP6]]
516+
; RV32-NEXT: [[TMP11:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP7]]
517+
; RV32-NEXT: [[TMP0:%.*]] = load i7, ptr [[ARRAYIDX_B]], align 1
518+
; RV32-NEXT: [[TMP13:%.*]] = load i7, ptr [[TMP9]], align 1
519+
; RV32-NEXT: [[TMP14:%.*]] = load i7, ptr [[TMP10]], align 1
520+
; RV32-NEXT: [[TMP15:%.*]] = load i7, ptr [[TMP11]], align 1
521+
; RV32-NEXT: [[TMP16:%.*]] = insertelement <4 x i7> poison, i7 [[TMP0]], i32 0
522+
; RV32-NEXT: [[TMP17:%.*]] = insertelement <4 x i7> [[TMP16]], i7 [[TMP13]], i32 1
523+
; RV32-NEXT: [[TMP18:%.*]] = insertelement <4 x i7> [[TMP17]], i7 [[TMP14]], i32 2
524+
; RV32-NEXT: [[TMP19:%.*]] = insertelement <4 x i7> [[TMP18]], i7 [[TMP15]], i32 3
525+
; RV32-NEXT: [[TMP20:%.*]] = add <4 x i7> [[TMP19]], splat (i7 1)
526+
; RV32-NEXT: [[TMP21:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[IV_NEXT]]
527+
; RV32-NEXT: [[TMP22:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP5]]
528+
; RV32-NEXT: [[TMP23:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP6]]
529+
; RV32-NEXT: [[TMP24:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP7]]
530+
; RV32-NEXT: [[TMP25:%.*]] = extractelement <4 x i7> [[TMP20]], i32 0
531+
; RV32-NEXT: store i7 [[TMP25]], ptr [[TMP21]], align 1
532+
; RV32-NEXT: [[TMP26:%.*]] = extractelement <4 x i7> [[TMP20]], i32 1
533+
; RV32-NEXT: store i7 [[TMP26]], ptr [[TMP22]], align 1
534+
; RV32-NEXT: [[TMP27:%.*]] = extractelement <4 x i7> [[TMP20]], i32 2
535+
; RV32-NEXT: store i7 [[TMP27]], ptr [[TMP23]], align 1
536+
; RV32-NEXT: [[TMP28:%.*]] = extractelement <4 x i7> [[TMP20]], i32 3
537+
; RV32-NEXT: store i7 [[TMP28]], ptr [[TMP24]], align 1
538+
; RV32-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
539+
; RV32-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1020
540+
; RV32-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
541+
; RV32: [[MIDDLE_BLOCK]]:
542+
; RV32-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]]
543+
; RV32: [[SCALAR_PH]]:
544+
; RV32-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 3, %[[MIDDLE_BLOCK]] ], [ 1023, %[[ENTRY]] ]
545+
; RV32-NEXT: br label %[[FOR_BODY:.*]]
546+
; RV32: [[FOR_BODY]]:
547+
; RV32-NEXT: [[DEC_IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], %[[FOR_BODY]] ]
548+
; RV32-NEXT: [[IV_NEXT1]] = add nsw i64 [[DEC_IV1]], -1
549+
; RV32-NEXT: [[ARRAYIDX_B1:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[IV_NEXT1]]
550+
; RV32-NEXT: [[TMP30:%.*]] = load i7, ptr [[ARRAYIDX_B1]], align 1
551+
; RV32-NEXT: [[ADD:%.*]] = add i7 [[TMP30]], 1
552+
; RV32-NEXT: [[ARRAYIDX_A:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[IV_NEXT1]]
553+
; RV32-NEXT: store i7 [[ADD]], ptr [[ARRAYIDX_A]], align 1
554+
; RV32-NEXT: [[CMP:%.*]] = icmp ugt i64 [[DEC_IV1]], 1
555+
; RV32-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
556+
; RV32: [[EXIT]]:
557+
; RV32-NEXT: ret void
558+
;
559+
; RV64-UF2-LABEL: define void @vector_reverse_irregular_type(
560+
; RV64-UF2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {
561+
; RV64-UF2-NEXT: [[ENTRY:.*]]:
562+
; RV64-UF2-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
563+
; RV64-UF2: [[VECTOR_PH]]:
564+
; RV64-UF2-NEXT: br label %[[VECTOR_BODY:.*]]
565+
; RV64-UF2: [[VECTOR_BODY]]:
566+
; RV64-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
567+
; RV64-UF2-NEXT: [[OFFSET_IDX:%.*]] = sub i64 1023, [[INDEX]]
568+
; RV64-UF2-NEXT: [[TMP16:%.*]] = add i64 [[OFFSET_IDX]], 0
569+
; RV64-UF2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], -1
570+
; RV64-UF2-NEXT: [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], -2
571+
; RV64-UF2-NEXT: [[TMP24:%.*]] = add i64 [[OFFSET_IDX]], -3
572+
; RV64-UF2-NEXT: [[TMP25:%.*]] = add i64 [[OFFSET_IDX]], -4
573+
; RV64-UF2-NEXT: [[TMP42:%.*]] = add i64 [[OFFSET_IDX]], -5
574+
; RV64-UF2-NEXT: [[TMP43:%.*]] = add i64 [[OFFSET_IDX]], -6
575+
; RV64-UF2-NEXT: [[TMP50:%.*]] = add i64 [[OFFSET_IDX]], -7
576+
; RV64-UF2-NEXT: [[TMP1:%.*]] = add nsw i64 [[TMP16]], -1
577+
; RV64-UF2-NEXT: [[TMP2:%.*]] = add nsw i64 [[TMP0]], -1
578+
; RV64-UF2-NEXT: [[TMP51:%.*]] = add nsw i64 [[TMP17]], -1
579+
; RV64-UF2-NEXT: [[TMP11:%.*]] = add nsw i64 [[TMP24]], -1
580+
; RV64-UF2-NEXT: [[TMP59:%.*]] = add nsw i64 [[TMP25]], -1
581+
; RV64-UF2-NEXT: [[TMP13:%.*]] = add nsw i64 [[TMP42]], -1
582+
; RV64-UF2-NEXT: [[TMP14:%.*]] = add nsw i64 [[TMP43]], -1
583+
; RV64-UF2-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP50]], -1
584+
; RV64-UF2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP1]]
585+
; RV64-UF2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP2]]
586+
; RV64-UF2-NEXT: [[TMP18:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP51]]
587+
; RV64-UF2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP11]]
588+
; RV64-UF2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP59]]
589+
; RV64-UF2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP13]]
590+
; RV64-UF2-NEXT: [[TMP22:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP14]]
591+
; RV64-UF2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[TMP15]]
592+
; RV64-UF2-NEXT: [[TMP5:%.*]] = load i7, ptr [[TMP3]], align 1
593+
; RV64-UF2-NEXT: [[TMP6:%.*]] = load i7, ptr [[TMP4]], align 1
594+
; RV64-UF2-NEXT: [[TMP26:%.*]] = load i7, ptr [[TMP18]], align 1
595+
; RV64-UF2-NEXT: [[TMP27:%.*]] = load i7, ptr [[TMP19]], align 1
596+
; RV64-UF2-NEXT: [[TMP28:%.*]] = insertelement <4 x i7> poison, i7 [[TMP5]], i32 0
597+
; RV64-UF2-NEXT: [[TMP29:%.*]] = insertelement <4 x i7> [[TMP28]], i7 [[TMP6]], i32 1
598+
; RV64-UF2-NEXT: [[TMP30:%.*]] = insertelement <4 x i7> [[TMP29]], i7 [[TMP26]], i32 2
599+
; RV64-UF2-NEXT: [[TMP31:%.*]] = insertelement <4 x i7> [[TMP30]], i7 [[TMP27]], i32 3
600+
; RV64-UF2-NEXT: [[TMP32:%.*]] = load i7, ptr [[TMP20]], align 1
601+
; RV64-UF2-NEXT: [[TMP33:%.*]] = load i7, ptr [[TMP21]], align 1
602+
; RV64-UF2-NEXT: [[TMP34:%.*]] = load i7, ptr [[TMP22]], align 1
603+
; RV64-UF2-NEXT: [[TMP35:%.*]] = load i7, ptr [[TMP23]], align 1
604+
; RV64-UF2-NEXT: [[TMP36:%.*]] = insertelement <4 x i7> poison, i7 [[TMP32]], i32 0
605+
; RV64-UF2-NEXT: [[TMP37:%.*]] = insertelement <4 x i7> [[TMP36]], i7 [[TMP33]], i32 1
606+
; RV64-UF2-NEXT: [[TMP38:%.*]] = insertelement <4 x i7> [[TMP37]], i7 [[TMP34]], i32 2
607+
; RV64-UF2-NEXT: [[TMP39:%.*]] = insertelement <4 x i7> [[TMP38]], i7 [[TMP35]], i32 3
608+
; RV64-UF2-NEXT: [[TMP40:%.*]] = add <4 x i7> [[TMP31]], splat (i7 1)
609+
; RV64-UF2-NEXT: [[TMP41:%.*]] = add <4 x i7> [[TMP39]], splat (i7 1)
610+
; RV64-UF2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP1]]
611+
; RV64-UF2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP2]]
612+
; RV64-UF2-NEXT: [[TMP44:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP51]]
613+
; RV64-UF2-NEXT: [[TMP45:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP11]]
614+
; RV64-UF2-NEXT: [[TMP46:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP59]]
615+
; RV64-UF2-NEXT: [[TMP47:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP13]]
616+
; RV64-UF2-NEXT: [[TMP48:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP14]]
617+
; RV64-UF2-NEXT: [[TMP49:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[TMP15]]
618+
; RV64-UF2-NEXT: [[TMP7:%.*]] = extractelement <4 x i7> [[TMP40]], i32 0
619+
; RV64-UF2-NEXT: store i7 [[TMP7]], ptr [[TMP9]], align 1
620+
; RV64-UF2-NEXT: [[TMP8:%.*]] = extractelement <4 x i7> [[TMP40]], i32 1
621+
; RV64-UF2-NEXT: store i7 [[TMP8]], ptr [[TMP10]], align 1
622+
; RV64-UF2-NEXT: [[TMP52:%.*]] = extractelement <4 x i7> [[TMP40]], i32 2
623+
; RV64-UF2-NEXT: store i7 [[TMP52]], ptr [[TMP44]], align 1
624+
; RV64-UF2-NEXT: [[TMP53:%.*]] = extractelement <4 x i7> [[TMP40]], i32 3
625+
; RV64-UF2-NEXT: store i7 [[TMP53]], ptr [[TMP45]], align 1
626+
; RV64-UF2-NEXT: [[TMP54:%.*]] = extractelement <4 x i7> [[TMP41]], i32 0
627+
; RV64-UF2-NEXT: store i7 [[TMP54]], ptr [[TMP46]], align 1
628+
; RV64-UF2-NEXT: [[TMP55:%.*]] = extractelement <4 x i7> [[TMP41]], i32 1
629+
; RV64-UF2-NEXT: store i7 [[TMP55]], ptr [[TMP47]], align 1
630+
; RV64-UF2-NEXT: [[TMP56:%.*]] = extractelement <4 x i7> [[TMP41]], i32 2
631+
; RV64-UF2-NEXT: store i7 [[TMP56]], ptr [[TMP48]], align 1
632+
; RV64-UF2-NEXT: [[TMP57:%.*]] = extractelement <4 x i7> [[TMP41]], i32 3
633+
; RV64-UF2-NEXT: store i7 [[TMP57]], ptr [[TMP49]], align 1
634+
; RV64-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
635+
; RV64-UF2-NEXT: [[TMP58:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1016
636+
; RV64-UF2-NEXT: br i1 [[TMP58]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
637+
; RV64-UF2: [[MIDDLE_BLOCK]]:
638+
; RV64-UF2-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]]
639+
; RV64-UF2: [[SCALAR_PH]]:
640+
; RV64-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 7, %[[MIDDLE_BLOCK]] ], [ 1023, %[[ENTRY]] ]
641+
; RV64-UF2-NEXT: br label %[[FOR_BODY:.*]]
642+
; RV64-UF2: [[FOR_BODY]]:
643+
; RV64-UF2-NEXT: [[DEC_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
644+
; RV64-UF2-NEXT: [[IV_NEXT]] = add nsw i64 [[DEC_IV]], -1
645+
; RV64-UF2-NEXT: [[ARRAYIDX_B:%.*]] = getelementptr inbounds i7, ptr [[B]], i64 [[IV_NEXT]]
646+
; RV64-UF2-NEXT: [[TMP12:%.*]] = load i7, ptr [[ARRAYIDX_B]], align 1
647+
; RV64-UF2-NEXT: [[ADD:%.*]] = add i7 [[TMP12]], 1
648+
; RV64-UF2-NEXT: [[ARRAYIDX_A:%.*]] = getelementptr inbounds i7, ptr [[A]], i64 [[IV_NEXT]]
649+
; RV64-UF2-NEXT: store i7 [[ADD]], ptr [[ARRAYIDX_A]], align 1
650+
; RV64-UF2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[DEC_IV]], 1
651+
; RV64-UF2-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
652+
; RV64-UF2: [[EXIT]]:
653+
; RV64-UF2-NEXT: ret void
654+
;
655+
entry:
656+
br label %for.body
657+
658+
for.body:
659+
%dec.iv = phi i64 [ 1023, %entry ], [ %iv.next, %for.body ]
660+
%iv.next = add nsw i64 %dec.iv, -1
661+
%arrayidx.b = getelementptr inbounds i7, ptr %B, i64 %iv.next
662+
%0 = load i7, ptr %arrayidx.b, align 1
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%add = add i7 %0, 1
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%arrayidx.a = getelementptr inbounds i7, ptr %A, i64 %iv.next
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store i7 %add, ptr %arrayidx.a, align 1
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%cmp = icmp ugt i64 %dec.iv, 1
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br i1 %cmp, label %for.body, label %exit, !llvm.loop !4
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exit:
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ret void
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}
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!0 = distinct !{!0, !1, !2, !3}
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!1 = !{!"llvm.loop.vectorize.width", i32 4}
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!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!3 = !{!"llvm.loop.vectorize.enable", i1 true}
677+
!4 = distinct !{!4, !1, !3}

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