[DAG] Fold (bitwiseop X, (add (not Y), Z)) -> (bitwiseop X, (not (sub Y, Z))). #141476
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@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-llvm-selectiondag Author: Xu Zhang (simonzgx) ChangesFull diff: https://github.com/llvm/llvm-project/pull/141476.diff 1 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index efaa8bd4a7950..31fbab23e4fcf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7528,6 +7528,13 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
return DAG.getNode(ISD::AND, DL, VT, X,
DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT));
+ // a bitwiseop (~b + c) -> a bitwiseop ~(b - c).
+ // Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z)))
+ if (sd_match(N, m_And(m_Value(X), m_Add(m_Value(NotY), m_Value(Z)))) &&
+ sd_match(NotY, m_Not(m_Value(Y))) &&
+ (TLI.hasAndNot(SDValue(N, 0)) || NotY->hasOneUse())) {
+ return DAG.getNode(ISD::AND, DL, VT, X, DAG.getNOT(DL, DAG.getNode(ISD::SUB, DL, VT, Y, Z), VT));
+ }
// Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction
// If we are shifting down an extended sign bit, see if we can simplify
// this to shifting the MSB directly to expose further simplifications.
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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As well as |
RKSimon
reviewed
May 27, 2025
Yes, there are some failed UT that need fixing and some new ones to add. I'm still working on both and will submit soon. |
RKSimon
reviewed
May 29, 2025
RKSimon
reviewed
May 29, 2025
simonzgx
changed the title
RKSimon
reviewed
May 31, 2025
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 | ||
| ; RUN: llc < %s -mtriple=aarch64-linux | FileCheck %s | ||
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| define i8 @andnot_add_with_neg_i8(i8 %0, i8 %1) { |
There was a problem hiding this comment.
(style) if you can its preferred to avoid numbered variables (also means you can drop the entry: labels).
RKSimon
reviewed
Jun 1, 2025
| @@ -11609,6 +11625,28 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N) { | |||
| return DAG.getNode(FloorISD, SDLoc(N), N->getValueType(0), {A, B}); | |||
| } | |||
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| SDValue DAGCombiner::foldBitwiseOpWithNeg(SDNode *N, const SDLoc &DL, EVT VT) { | |||
| if (!TLI.hasAndNot(SDValue(N, 0))) | |||
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We're checking for ANDNOT instructions but we're also folding to ORNOT and XORNOT patterns?
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Fixes #140639