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[SelectionDAG] Change computeAliasing signature from optional<uint64> to LocationSize. (llvm#83017)
This is another smaller step of llvm#70452, changing the signature of computeAliasing() from optional<uint64_t> to LocationSize, and follow-up changes in DAGCombiner::mayAlias(). There are some test change due to the previous AA->isNoAlias call incorrectly using an unknown size (~UINT64_T(0)). This should then be improved again in llvm#70452 when the types are known to be scalable. (cherry picked from commit 6e41d60)
1 parent 461274b commit 98fdd57

8 files changed

+102
-110
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#ifndef LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
1010
#define LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
1111

12+
#include "llvm/Analysis/MemoryLocation.h"
1213
#include "llvm/CodeGen/SelectionDAGNodes.h"
1314
#include <cstdint>
1415

@@ -81,10 +82,8 @@ class BaseIndexOffset {
8182

8283
// Returns true `Op0` and `Op1` can be proven to alias/not alias, in
8384
// which case `IsAlias` is set to true/false.
84-
static bool computeAliasing(const SDNode *Op0,
85-
const std::optional<int64_t> NumBytes0,
86-
const SDNode *Op1,
87-
const std::optional<int64_t> NumBytes1,
85+
static bool computeAliasing(const SDNode *Op0, const LocationSize NumBytes0,
86+
const SDNode *Op1, const LocationSize NumBytes1,
8887
const SelectionDAG &DAG, bool &IsAlias);
8988

9089
/// Parses tree in N for base, index, offset addresses.

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -27849,7 +27849,7 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2784927849
bool IsAtomic;
2785027850
SDValue BasePtr;
2785127851
int64_t Offset;
27852-
std::optional<int64_t> NumBytes;
27852+
LocationSize NumBytes;
2785327853
MachineMemOperand *MMO;
2785427854
};
2785527855

@@ -27868,21 +27868,24 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2786827868
LSN->isAtomic(),
2786927869
LSN->getBasePtr(),
2787027870
Offset /*base offset*/,
27871-
std::optional<int64_t>(Size),
27871+
Size != ~UINT64_C(0) ? LocationSize::precise(Size)
27872+
: LocationSize::beforeOrAfterPointer(),
2787227873
LSN->getMemOperand()};
2787327874
}
2787427875
if (const auto *LN = cast<LifetimeSDNode>(N))
2787527876
return {false /*isVolatile*/,
2787627877
/*isAtomic*/ false,
2787727878
LN->getOperand(1),
2787827879
(LN->hasOffset()) ? LN->getOffset() : 0,
27879-
(LN->hasOffset()) ? std::optional<int64_t>(LN->getSize())
27880-
: std::optional<int64_t>(),
27880+
(LN->hasOffset()) ? LocationSize::precise(LN->getSize())
27881+
: LocationSize::beforeOrAfterPointer(),
2788127882
(MachineMemOperand *)nullptr};
2788227883
// Default.
2788327884
return {false /*isvolatile*/,
27884-
/*isAtomic*/ false, SDValue(),
27885-
(int64_t)0 /*offset*/, std::optional<int64_t>() /*size*/,
27885+
/*isAtomic*/ false,
27886+
SDValue(),
27887+
(int64_t)0 /*offset*/,
27888+
LocationSize::beforeOrAfterPointer() /*size*/,
2788627889
(MachineMemOperand *)nullptr};
2788727890
};
2788827891

@@ -27937,18 +27940,20 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2793727940
int64_t SrcValOffset1 = MUC1.MMO->getOffset();
2793827941
Align OrigAlignment0 = MUC0.MMO->getBaseAlign();
2793927942
Align OrigAlignment1 = MUC1.MMO->getBaseAlign();
27940-
auto &Size0 = MUC0.NumBytes;
27941-
auto &Size1 = MUC1.NumBytes;
27943+
LocationSize Size0 = MUC0.NumBytes;
27944+
LocationSize Size1 = MUC1.NumBytes;
2794227945
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27943-
Size0.has_value() && Size1.has_value() && *Size0 == *Size1 &&
27944-
OrigAlignment0 > *Size0 && SrcValOffset0 % *Size0 == 0 &&
27945-
SrcValOffset1 % *Size1 == 0) {
27946+
Size0.hasValue() && Size1.hasValue() && Size0 == Size1 &&
27947+
OrigAlignment0 > Size0.getValue() &&
27948+
SrcValOffset0 % Size0.getValue() == 0 &&
27949+
SrcValOffset1 % Size1.getValue() == 0) {
2794627950
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
2794727951
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
2794827952

2794927953
// There is no overlap between these relatively aligned accesses of
2795027954
// similar size. Return no alias.
27951-
if ((OffAlign0 + *Size0) <= OffAlign1 || (OffAlign1 + *Size1) <= OffAlign0)
27955+
if ((OffAlign0 + (int64_t)Size0.getValue()) <= OffAlign1 ||
27956+
(OffAlign1 + (int64_t)Size1.getValue()) <= OffAlign0)
2795227957
return false;
2795327958
}
2795427959

@@ -27961,12 +27966,12 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2796127966
UseAA = false;
2796227967
#endif
2796327968

27964-
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() && Size0 &&
27965-
Size1) {
27969+
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() &&
27970+
Size0.hasValue() && Size1.hasValue()) {
2796627971
// Use alias analysis information.
2796727972
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
27968-
int64_t Overlap0 = *Size0 + SrcValOffset0 - MinOffset;
27969-
int64_t Overlap1 = *Size1 + SrcValOffset1 - MinOffset;
27973+
int64_t Overlap0 = Size0.getValue() + SrcValOffset0 - MinOffset;
27974+
int64_t Overlap1 = Size1.getValue() + SrcValOffset1 - MinOffset;
2797027975
if (AA->isNoAlias(
2797127976
MemoryLocation(MUC0.MMO->getValue(), Overlap0,
2797227977
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()),

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,10 @@ bool BaseIndexOffset::equalBaseIndex(const BaseIndexOffset &Other,
9191
}
9292

9393
bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
94-
const std::optional<int64_t> NumBytes0,
94+
const LocationSize NumBytes0,
9595
const SDNode *Op1,
96-
const std::optional<int64_t> NumBytes1,
96+
const LocationSize NumBytes1,
9797
const SelectionDAG &DAG, bool &IsAlias) {
98-
9998
BaseIndexOffset BasePtr0 = match(Op0, DAG);
10099
if (!BasePtr0.getBase().getNode())
101100
return false;
@@ -105,27 +104,26 @@ bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
105104
return false;
106105

107106
int64_t PtrDiff;
108-
if (NumBytes0 && NumBytes1 &&
109-
BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) {
107+
if (BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) {
110108
// If the size of memory access is unknown, do not use it to analysis.
111109
// One example of unknown size memory access is to load/store scalable
112110
// vector objects on the stack.
113111
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
114112
// following situations arise:
115-
if (PtrDiff >= 0 &&
116-
*NumBytes0 != static_cast<int64_t>(MemoryLocation::UnknownSize)) {
113+
if (PtrDiff >= 0 && NumBytes0.hasValue() && !NumBytes0.isScalable()) {
117114
// [----BasePtr0----]
118115
// [---BasePtr1--]
119116
// ========PtrDiff========>
120-
IsAlias = !(*NumBytes0 <= PtrDiff);
117+
IsAlias = !(static_cast<int64_t>(NumBytes0.getValue().getFixedValue()) <=
118+
PtrDiff);
121119
return true;
122120
}
123-
if (PtrDiff < 0 &&
124-
*NumBytes1 != static_cast<int64_t>(MemoryLocation::UnknownSize)) {
121+
if (PtrDiff < 0 && NumBytes1.hasValue() && !NumBytes1.isScalable()) {
125122
// [----BasePtr0----]
126123
// [---BasePtr1--]
127124
// =====(-PtrDiff)====>
128-
IsAlias = !((PtrDiff + *NumBytes1) <= 0);
125+
IsAlias = !((PtrDiff + static_cast<int64_t>(
126+
NumBytes1.getValue().getFixedValue())) <= 0);
129127
return true;
130128
}
131129
return false;

‎llvm/test/CodeGen/AArch64/alloca-load-store-scalable-array.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,12 @@ define void @array_1D(ptr %addr) #0 {
1414
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
1515
; CHECK-NEXT: .cfi_offset w29, -16
1616
; CHECK-NEXT: ptrue p0.d
17-
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
18-
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #2, mul vl]
19-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0, #1, mul vl]
20-
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
21-
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #2, mul vl]
22-
; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
17+
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #2, mul vl]
18+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
19+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
20+
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
21+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #1, mul vl]
22+
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
2323
; CHECK-NEXT: addvl sp, sp, #3
2424
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
2525
; CHECK-NEXT: ret
@@ -81,18 +81,18 @@ define void @array_2D(ptr %addr) #0 {
8181
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 48 * VG
8282
; CHECK-NEXT: .cfi_offset w29, -16
8383
; CHECK-NEXT: ptrue p0.d
84-
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
85-
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #5, mul vl]
86-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0, #1, mul vl]
87-
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x0, #4, mul vl]
88-
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x0, #2, mul vl]
89-
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x0, #3, mul vl]
90-
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
91-
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #5, mul vl]
92-
; CHECK-NEXT: st1d { z3.d }, p0, [sp, #4, mul vl]
93-
; CHECK-NEXT: st1d { z5.d }, p0, [sp, #3, mul vl]
94-
; CHECK-NEXT: st1d { z4.d }, p0, [sp, #2, mul vl]
95-
; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
84+
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #5, mul vl]
85+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #4, mul vl]
86+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
87+
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x0, #3, mul vl]
88+
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x0, #1, mul vl]
89+
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x0, #2, mul vl]
90+
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #5, mul vl]
91+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #4, mul vl]
92+
; CHECK-NEXT: st1d { z3.d }, p0, [sp, #3, mul vl]
93+
; CHECK-NEXT: st1d { z5.d }, p0, [sp, #2, mul vl]
94+
; CHECK-NEXT: st1d { z4.d }, p0, [sp, #1, mul vl]
95+
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
9696
; CHECK-NEXT: addvl sp, sp, #6
9797
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
9898
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@ define void @test(ptr %addr) #0 {
1313
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
1414
; CHECK-NEXT: .cfi_offset w29, -16
1515
; CHECK-NEXT: ptrue p0.d
16-
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
17-
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #2, mul vl]
18-
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0, #1, mul vl]
19-
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
20-
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #2, mul vl]
21-
; CHECK-NEXT: st1d { z2.d }, p0, [sp, #1, mul vl]
16+
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #2, mul vl]
17+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
18+
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
19+
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
20+
; CHECK-NEXT: st1d { z1.d }, p0, [sp, #1, mul vl]
21+
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
2222
; CHECK-NEXT: addvl sp, sp, #3
2323
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
2424
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,15 +18,15 @@ define void @test(ptr %addr) {
1818
; CHECK-NEXT: add a2, a0, a1
1919
; CHECK-NEXT: vl1re64.v v8, (a2)
2020
; CHECK-NEXT: slli a2, a1, 1
21-
; CHECK-NEXT: vl1re64.v v9, (a0)
22-
; CHECK-NEXT: add a0, a0, a2
21+
; CHECK-NEXT: add a3, a0, a2
22+
; CHECK-NEXT: vl1re64.v v9, (a3)
2323
; CHECK-NEXT: vl1re64.v v10, (a0)
2424
; CHECK-NEXT: addi a0, sp, 16
25-
; CHECK-NEXT: vs1r.v v9, (a0)
2625
; CHECK-NEXT: add a2, a0, a2
27-
; CHECK-NEXT: vs1r.v v10, (a2)
28-
; CHECK-NEXT: add a0, a0, a1
29-
; CHECK-NEXT: vs1r.v v8, (a0)
26+
; CHECK-NEXT: vs1r.v v9, (a2)
27+
; CHECK-NEXT: add a1, a0, a1
28+
; CHECK-NEXT: vs1r.v v8, (a1)
29+
; CHECK-NEXT: vs1r.v v10, (a0)
3030
; CHECK-NEXT: csrrs a0, vlenb, zero
3131
; CHECK-NEXT: slli a0, a0, 2
3232
; CHECK-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@ define <vscale x 1 x double> @test(%struct.test* %addr, i64 %vl) {
1616
; CHECK-NEXT: sub sp, sp, a2
1717
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
1818
; CHECK-NEXT: csrrs a2, vlenb, zero
19-
; CHECK-NEXT: vl1re64.v v8, (a0)
20-
; CHECK-NEXT: add a0, a0, a2
19+
; CHECK-NEXT: add a3, a0, a2
20+
; CHECK-NEXT: vl1re64.v v8, (a3)
2121
; CHECK-NEXT: vl1re64.v v9, (a0)
2222
; CHECK-NEXT: addi a0, sp, 16
23-
; CHECK-NEXT: vs1r.v v8, (a0)
2423
; CHECK-NEXT: add a2, a0, a2
25-
; CHECK-NEXT: vs1r.v v9, (a2)
24+
; CHECK-NEXT: vs1r.v v8, (a2)
25+
; CHECK-NEXT: vs1r.v v9, (a0)
2626
; CHECK-NEXT: vl1re64.v v8, (a2)
2727
; CHECK-NEXT: vl1re64.v v9, (a0)
2828
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma

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