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[RISCV] Use MF8 for vmv.s.x and vmv.x.s pseudos
1 parent 8404406 commit 59bd222

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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -801,6 +801,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
801801

802802
RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags);
803803

804+
if (isScalarInsertInstr(MI) || isScalarExtractInstr(MI))
805+
VLMul = RISCVII::LMUL_F8;
806+
804807
unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm();
805808
// A Log2SEW of 0 is an operation on mask registers only.
806809
unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;

‎llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
88
; CHECK-LABEL: extractelt_nxv1f16_0:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
10+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
1111
; CHECK-NEXT: vfmv.f.s fa0, v8
1212
; CHECK-NEXT: ret
1313
%r = extractelement <vscale x 1 x half> %v, i32 0
@@ -39,7 +39,7 @@ define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 zeroext %idx) {
3939
define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
4040
; CHECK-LABEL: extractelt_nxv2f16_0:
4141
; CHECK: # %bb.0:
42-
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
42+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
4343
; CHECK-NEXT: vfmv.f.s fa0, v8
4444
; CHECK-NEXT: ret
4545
%r = extractelement <vscale x 2 x half> %v, i32 0
@@ -71,7 +71,7 @@ define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 zeroext %idx) {
7171
define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
7272
; CHECK-LABEL: extractelt_nxv4f16_0:
7373
; CHECK: # %bb.0:
74-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
74+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
7575
; CHECK-NEXT: vfmv.f.s fa0, v8
7676
; CHECK-NEXT: ret
7777
%r = extractelement <vscale x 4 x half> %v, i32 0
@@ -103,7 +103,7 @@ define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 zeroext %idx) {
103103
define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
104104
; CHECK-LABEL: extractelt_nxv8f16_0:
105105
; CHECK: # %bb.0:
106-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
106+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
107107
; CHECK-NEXT: vfmv.f.s fa0, v8
108108
; CHECK-NEXT: ret
109109
%r = extractelement <vscale x 8 x half> %v, i32 0
@@ -135,7 +135,7 @@ define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 zeroext %idx) {
135135
define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
136136
; CHECK-LABEL: extractelt_nxv16f16_0:
137137
; CHECK: # %bb.0:
138-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
138+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
139139
; CHECK-NEXT: vfmv.f.s fa0, v8
140140
; CHECK-NEXT: ret
141141
%r = extractelement <vscale x 16 x half> %v, i32 0
@@ -167,7 +167,7 @@ define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 zeroext %idx)
167167
define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
168168
; CHECK-LABEL: extractelt_nxv32f16_0:
169169
; CHECK: # %bb.0:
170-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
170+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
171171
; CHECK-NEXT: vfmv.f.s fa0, v8
172172
; CHECK-NEXT: ret
173173
%r = extractelement <vscale x 32 x half> %v, i32 0
@@ -199,7 +199,7 @@ define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 zeroext %idx)
199199
define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
200200
; CHECK-LABEL: extractelt_nxv1f32_0:
201201
; CHECK: # %bb.0:
202-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
202+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
203203
; CHECK-NEXT: vfmv.f.s fa0, v8
204204
; CHECK-NEXT: ret
205205
%r = extractelement <vscale x 1 x float> %v, i32 0
@@ -231,7 +231,7 @@ define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 zeroext %idx)
231231
define float @extractelt_nxv2f32_0(<vscale x 2 x float> %v) {
232232
; CHECK-LABEL: extractelt_nxv2f32_0:
233233
; CHECK: # %bb.0:
234-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
234+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
235235
; CHECK-NEXT: vfmv.f.s fa0, v8
236236
; CHECK-NEXT: ret
237237
%r = extractelement <vscale x 2 x float> %v, i32 0
@@ -263,7 +263,7 @@ define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 zeroext %idx)
263263
define float @extractelt_nxv4f32_0(<vscale x 4 x float> %v) {
264264
; CHECK-LABEL: extractelt_nxv4f32_0:
265265
; CHECK: # %bb.0:
266-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
266+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
267267
; CHECK-NEXT: vfmv.f.s fa0, v8
268268
; CHECK-NEXT: ret
269269
%r = extractelement <vscale x 4 x float> %v, i32 0
@@ -295,7 +295,7 @@ define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 zeroext %idx)
295295
define float @extractelt_nxv8f32_0(<vscale x 8 x float> %v) {
296296
; CHECK-LABEL: extractelt_nxv8f32_0:
297297
; CHECK: # %bb.0:
298-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
298+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
299299
; CHECK-NEXT: vfmv.f.s fa0, v8
300300
; CHECK-NEXT: ret
301301
%r = extractelement <vscale x 8 x float> %v, i32 0
@@ -327,7 +327,7 @@ define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 zeroext %idx)
327327
define float @extractelt_nxv16f32_0(<vscale x 16 x float> %v) {
328328
; CHECK-LABEL: extractelt_nxv16f32_0:
329329
; CHECK: # %bb.0:
330-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
330+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
331331
; CHECK-NEXT: vfmv.f.s fa0, v8
332332
; CHECK-NEXT: ret
333333
%r = extractelement <vscale x 16 x float> %v, i32 0
@@ -359,7 +359,7 @@ define float @extractelt_nxv16f32_idx(<vscale x 16 x float> %v, i32 zeroext %idx
359359
define double @extractelt_nxv1f64_0(<vscale x 1 x double> %v) {
360360
; CHECK-LABEL: extractelt_nxv1f64_0:
361361
; CHECK: # %bb.0:
362-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
362+
; CHECK-NEXT: vsetivli zero, 1, e64, mf8, ta, ma
363363
; CHECK-NEXT: vfmv.f.s fa0, v8
364364
; CHECK-NEXT: ret
365365
%r = extractelement <vscale x 1 x double> %v, i32 0
@@ -391,7 +391,7 @@ define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 zeroext %idx
391391
define double @extractelt_nxv2f64_0(<vscale x 2 x double> %v) {
392392
; CHECK-LABEL: extractelt_nxv2f64_0:
393393
; CHECK: # %bb.0:
394-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
394+
; CHECK-NEXT: vsetivli zero, 1, e64, mf8, ta, ma
395395
; CHECK-NEXT: vfmv.f.s fa0, v8
396396
; CHECK-NEXT: ret
397397
%r = extractelement <vscale x 2 x double> %v, i32 0
@@ -423,7 +423,7 @@ define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 zeroext %idx
423423
define double @extractelt_nxv4f64_0(<vscale x 4 x double> %v) {
424424
; CHECK-LABEL: extractelt_nxv4f64_0:
425425
; CHECK: # %bb.0:
426-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
426+
; CHECK-NEXT: vsetivli zero, 1, e64, mf8, ta, ma
427427
; CHECK-NEXT: vfmv.f.s fa0, v8
428428
; CHECK-NEXT: ret
429429
%r = extractelement <vscale x 4 x double> %v, i32 0
@@ -455,7 +455,7 @@ define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 zeroext %idx
455455
define double @extractelt_nxv8f64_0(<vscale x 8 x double> %v) {
456456
; CHECK-LABEL: extractelt_nxv8f64_0:
457457
; CHECK: # %bb.0:
458-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
458+
; CHECK-NEXT: vsetivli zero, 1, e64, mf8, ta, ma
459459
; CHECK-NEXT: vfmv.f.s fa0, v8
460460
; CHECK-NEXT: ret
461461
%r = extractelement <vscale x 8 x double> %v, i32 0
@@ -567,7 +567,7 @@ define float @extractelt_fmul_nxv4f32_splat(<vscale x 4 x float> %x) {
567567
define float @extractelt_fdiv_nxv4f32_splat(<vscale x 4 x float> %x) {
568568
; CHECK-LABEL: extractelt_fdiv_nxv4f32_splat:
569569
; CHECK: # %bb.0:
570-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
570+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
571571
; CHECK-NEXT: vfmv.f.s fa5, v8
572572
; CHECK-NEXT: lui a0, 263168
573573
; CHECK-NEXT: fmv.w.x fa4, a0
@@ -583,7 +583,7 @@ define float @extractelt_fdiv_nxv4f32_splat(<vscale x 4 x float> %x) {
583583
define double @extractelt_nxv16f64_0(<vscale x 16 x double> %v) {
584584
; CHECK-LABEL: extractelt_nxv16f64_0:
585585
; CHECK: # %bb.0:
586-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
586+
; CHECK-NEXT: vsetivli zero, 1, e64, mf8, ta, ma
587587
; CHECK-NEXT: vfmv.f.s fa0, v8
588588
; CHECK-NEXT: ret
589589
%r = extractelement <vscale x 16 x double> %v, i32 0

‎llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
4040
define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
4141
; CHECK-LABEL: extractelt_nxv2i8_0:
4242
; CHECK: # %bb.0:
43-
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
43+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
4444
; CHECK-NEXT: vmv.x.s a0, v8
4545
; CHECK-NEXT: ret
4646
%r = extractelement <vscale x 2 x i8> %v, i32 0
@@ -72,7 +72,7 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
7272
define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
7373
; CHECK-LABEL: extractelt_nxv4i8_0:
7474
; CHECK: # %bb.0:
75-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
75+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
7676
; CHECK-NEXT: vmv.x.s a0, v8
7777
; CHECK-NEXT: ret
7878
%r = extractelement <vscale x 4 x i8> %v, i32 0
@@ -104,7 +104,7 @@ define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 %idx) {
104104
define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
105105
; CHECK-LABEL: extractelt_nxv8i8_0:
106106
; CHECK: # %bb.0:
107-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
107+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
108108
; CHECK-NEXT: vmv.x.s a0, v8
109109
; CHECK-NEXT: ret
110110
%r = extractelement <vscale x 8 x i8> %v, i32 0
@@ -136,7 +136,7 @@ define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 %idx) {
136136
define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
137137
; CHECK-LABEL: extractelt_nxv16i8_0:
138138
; CHECK: # %bb.0:
139-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
139+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
140140
; CHECK-NEXT: vmv.x.s a0, v8
141141
; CHECK-NEXT: ret
142142
%r = extractelement <vscale x 16 x i8> %v, i32 0
@@ -168,7 +168,7 @@ define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 %idx) {
168168
define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
169169
; CHECK-LABEL: extractelt_nxv32i8_0:
170170
; CHECK: # %bb.0:
171-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
171+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
172172
; CHECK-NEXT: vmv.x.s a0, v8
173173
; CHECK-NEXT: ret
174174
%r = extractelement <vscale x 32 x i8> %v, i32 0
@@ -200,7 +200,7 @@ define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 %idx) {
200200
define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
201201
; CHECK-LABEL: extractelt_nxv64i8_0:
202202
; CHECK: # %bb.0:
203-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
203+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
204204
; CHECK-NEXT: vmv.x.s a0, v8
205205
; CHECK-NEXT: ret
206206
%r = extractelement <vscale x 64 x i8> %v, i32 0
@@ -232,7 +232,7 @@ define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {
232232
define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
233233
; CHECK-LABEL: extractelt_nxv1i16_0:
234234
; CHECK: # %bb.0:
235-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
235+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
236236
; CHECK-NEXT: vmv.x.s a0, v8
237237
; CHECK-NEXT: ret
238238
%r = extractelement <vscale x 1 x i16> %v, i32 0
@@ -264,7 +264,7 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
264264
define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
265265
; CHECK-LABEL: extractelt_nxv2i16_0:
266266
; CHECK: # %bb.0:
267-
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
267+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
268268
; CHECK-NEXT: vmv.x.s a0, v8
269269
; CHECK-NEXT: ret
270270
%r = extractelement <vscale x 2 x i16> %v, i32 0
@@ -296,7 +296,7 @@ define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 %idx) {
296296
define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
297297
; CHECK-LABEL: extractelt_nxv4i16_0:
298298
; CHECK: # %bb.0:
299-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
299+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
300300
; CHECK-NEXT: vmv.x.s a0, v8
301301
; CHECK-NEXT: ret
302302
%r = extractelement <vscale x 4 x i16> %v, i32 0
@@ -328,7 +328,7 @@ define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 %idx) {
328328
define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
329329
; CHECK-LABEL: extractelt_nxv8i16_0:
330330
; CHECK: # %bb.0:
331-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
331+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
332332
; CHECK-NEXT: vmv.x.s a0, v8
333333
; CHECK-NEXT: ret
334334
%r = extractelement <vscale x 8 x i16> %v, i32 0
@@ -360,7 +360,7 @@ define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 %idx) {
360360
define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
361361
; CHECK-LABEL: extractelt_nxv16i16_0:
362362
; CHECK: # %bb.0:
363-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
363+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
364364
; CHECK-NEXT: vmv.x.s a0, v8
365365
; CHECK-NEXT: ret
366366
%r = extractelement <vscale x 16 x i16> %v, i32 0
@@ -392,7 +392,7 @@ define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 %idx) {
392392
define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
393393
; CHECK-LABEL: extractelt_nxv32i16_0:
394394
; CHECK: # %bb.0:
395-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
395+
; CHECK-NEXT: vsetivli zero, 1, e16, mf8, ta, ma
396396
; CHECK-NEXT: vmv.x.s a0, v8
397397
; CHECK-NEXT: ret
398398
%r = extractelement <vscale x 32 x i16> %v, i32 0
@@ -424,7 +424,7 @@ define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {
424424
define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
425425
; CHECK-LABEL: extractelt_nxv1i32_0:
426426
; CHECK: # %bb.0:
427-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
427+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
428428
; CHECK-NEXT: vmv.x.s a0, v8
429429
; CHECK-NEXT: ret
430430
%r = extractelement <vscale x 1 x i32> %v, i32 0
@@ -456,7 +456,7 @@ define i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %idx) {
456456
define i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {
457457
; CHECK-LABEL: extractelt_nxv2i32_0:
458458
; CHECK: # %bb.0:
459-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
459+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
460460
; CHECK-NEXT: vmv.x.s a0, v8
461461
; CHECK-NEXT: ret
462462
%r = extractelement <vscale x 2 x i32> %v, i32 0
@@ -488,7 +488,7 @@ define i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %idx) {
488488
define i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {
489489
; CHECK-LABEL: extractelt_nxv4i32_0:
490490
; CHECK: # %bb.0:
491-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
491+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
492492
; CHECK-NEXT: vmv.x.s a0, v8
493493
; CHECK-NEXT: ret
494494
%r = extractelement <vscale x 4 x i32> %v, i32 0
@@ -520,7 +520,7 @@ define i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %idx) {
520520
define i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {
521521
; CHECK-LABEL: extractelt_nxv8i32_0:
522522
; CHECK: # %bb.0:
523-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
523+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
524524
; CHECK-NEXT: vmv.x.s a0, v8
525525
; CHECK-NEXT: ret
526526
%r = extractelement <vscale x 8 x i32> %v, i32 0
@@ -552,7 +552,7 @@ define i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %idx) {
552552
define i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {
553553
; CHECK-LABEL: extractelt_nxv16i32_0:
554554
; CHECK: # %bb.0:
555-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
555+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
556556
; CHECK-NEXT: vmv.x.s a0, v8
557557
; CHECK-NEXT: ret
558558
%r = extractelement <vscale x 16 x i32> %v, i32 0
@@ -816,7 +816,7 @@ define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
816816
;
817817
; RV32M-LABEL: extractelt_sdiv_nxv4i32_splat:
818818
; RV32M: # %bb.0:
819-
; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma
819+
; RV32M-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
820820
; RV32M-NEXT: vmv.x.s a0, v8
821821
; RV32M-NEXT: lui a1, 349525
822822
; RV32M-NEXT: addi a1, a1, 1366
@@ -845,7 +845,7 @@ define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
845845
;
846846
; RV32M-LABEL: extractelt_udiv_nxv4i32_splat:
847847
; RV32M: # %bb.0:
848-
; RV32M-NEXT: vsetivli zero, 1, e32, m1, ta, ma
848+
; RV32M-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
849849
; RV32M-NEXT: vmv.x.s a0, v8
850850
; RV32M-NEXT: lui a1, 349525
851851
; RV32M-NEXT: addi a1, a1, 1366
@@ -863,7 +863,7 @@ define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
863863
define i32 @extractelt_nxv32i32_0(<vscale x 32 x i32> %v) {
864864
; CHECK-LABEL: extractelt_nxv32i32_0:
865865
; CHECK: # %bb.0:
866-
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
866+
; CHECK-NEXT: vsetivli zero, 1, e32, mf8, ta, ma
867867
; CHECK-NEXT: vmv.x.s a0, v8
868868
; CHECK-NEXT: ret
869869
%r = extractelement <vscale x 32 x i32> %v, i32 0

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