[RISCV] Add -verify-machineinstrs to RISCVInsertVSETVLI MIR tests. NFC

Now that we're working with LiveIntervals, make sure that they're correct.

Author: lukel97

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=v \
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -verify-machineinstrs \
 # RUN:     -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s
 
 --- |

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=liveintervals,riscv-insert-vsetvli \
-# RUN:     | FileCheck %s
+# RUN:     -verify-machineinstrs | FileCheck %s
 
 --- |
   source_filename = "vsetvli-insert.ll"