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‎llvm/lib/Target/MC6809/AsmParser/MC6809AsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ class MC6809AsmParser : public MCTargetAsmParser {
302302
///
303303
/// On failure, the target parser is responsible for emitting a diagnostic
304304
/// explaining the match failure.
305-
bool MatchAndEmitInstruction(SMLoc Loc, unsigned & /*Opcode*/, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) override {
305+
bool matchAndEmitInstruction(SMLoc Loc, unsigned & /*Opcode*/, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) override {
306306
MCInst Inst;
307307
unsigned MatchResult =
308308
// we always want ConvertToMapAndConstraints to be called
@@ -663,7 +663,7 @@ class MC6809AsmParser : public MCTargetAsmParser {
663663
return ParseStatus::NoMatch;
664664
}
665665

666-
bool ParseInstruction(ParseInstructionInfo & /*Info*/, StringRef Mnemonic, SMLoc NameLoc, OperandVector &Operands) override {
666+
bool parseInstruction(ParseInstructionInfo & /*Info*/, StringRef Mnemonic, SMLoc NameLoc, OperandVector &Operands) override {
667667
/*
668668
On 65xx family instructions, mnemonics and addressing modes take the form:
669669

‎llvm/lib/Target/MC6809/GISel/MC6809InstructionSelector.cpp

Lines changed: 20 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1334,51 +1334,27 @@ bool MC6809InstructionSelector::selectTrunc(MachineInstr &MI) {
13341334
#endif
13351335

13361336
bool MC6809InstructionSelector::selectUnMergeValues(MachineInstr &MI) {
1337-
LLVM_DEBUG(dbgs() << "OINQUE DEBUG " << __func__ << " : Enter : MI = "; MI.dump(););
1338-
MachineIRBuilder Builder(MI);
1337+
auto [Lo, Hi, Src] = MI.getFirst3Regs();
13391338

1340-
Register Lo = MI.getOperand(0).getReg();
1341-
Register Hi = MI.getOperand(1).getReg();
1342-
Register Src = MI.getOperand(2).getReg();
1343-
bool SplittingAQ = false;
1344-
1345-
// auto SrcConst = getIConstantVRegValWithLookThrough(Src, *MRI);
1346-
auto MaybeCopy = getDefIgnoringCopies(MI.getOperand(2).getReg(), *MRI);
1347-
dbgs() << "OINQUE DEBUG : " << __func__ << " : Gotcha? : Parent = "; MaybeCopy->dump();
1348-
if (MaybeCopy->isCopy()) {
1349-
dbgs() << "OINQUE DEBUG : " << __func__ << " : Gotcha! : isCopy()\n";
1350-
if (MaybeCopy->getOperand(1).isReg()) {
1351-
dbgs() << "OINQUE DEBUG : " << __func__ << " : Gotcha! : isReg()\n";
1352-
if (MaybeCopy->getOperand(1).getReg() == MC6809::AQ) {
1353-
SplittingAQ = true;
1354-
dbgs() << "OINQUE DEBUG : " << __func__ << " : Gotcha! : == AQ\n";
1355-
}
1356-
}
1357-
}
1358-
const unsigned Size = MRI->getType(Lo).getSizeInBits();
1359-
MachineInstrBuilder LoCopy;
1360-
MachineInstrBuilder HiCopy;
1361-
LoCopy = Builder.buildCopy(Lo, Src);
1362-
HiCopy = Builder.buildCopy(Hi, Src);
1363-
if (Size == 8) {
1364-
LoCopy->getOperand(1).setSubReg(MC6809::sub_lo_byte);
1365-
HiCopy->getOperand(1).setSubReg(MC6809::sub_hi_byte);
1366-
} else if (Size == 16) {
1367-
if (SplittingAQ) {
1368-
constrainOperandRegClass(LoCopy->getOperand(1), getRegClassForType());
1369-
LoCopy->getOperand(1);
1370-
HiCopy->getOperand(1).setSubReg(MC6809::sub_hi_word);
1371-
}
1372-
LoCopy->getOperand(1).setSubReg(MC6809::sub_lo_word);
1373-
HiCopy->getOperand(1).setSubReg(MC6809::sub_hi_word);
1374-
} else
1375-
return false;
1376-
constrainGenericOp(*LoCopy);
1377-
constrainGenericOp(*HiCopy);
1378-
LLVM_DEBUG(dbgs() << "OINQUE DEBUG " << __func__ << " : Exit : LoCopy = "; LoCopy->dump(););
1379-
LLVM_DEBUG(dbgs() << "OINQUE DEBUG " << __func__ << " : Exit : HiCopy = "; HiCopy->dump(););
1380-
MI.eraseFromParent();
1381-
return true;
1339+
MachineIRBuilder Builder(MI);
1340+
LLT SrcTy = MRI->getType(Src);
1341+
assert((SrcTy == S16 || SrcTy == S32) && "The Src of G_UNMERGE_VALUES must be S16 or S32");
1342+
1343+
MachineInstrBuilder LoCopy;
1344+
MachineInstrBuilder HiCopy;
1345+
LoCopy = Builder.buildCopy(Lo, Src);
1346+
HiCopy = Builder.buildCopy(Hi, Src);
1347+
if (SrcTy == S16) {
1348+
LoCopy->getOperand(1).setSubReg(MC6809::sub_lo_byte);
1349+
HiCopy->getOperand(1).setSubReg(MC6809::sub_hi_byte);
1350+
} else {
1351+
LoCopy->getOperand(1).setSubReg(MC6809::sub_lo_word);
1352+
HiCopy->getOperand(1).setSubReg(MC6809::sub_hi_word);
1353+
}
1354+
constrainGenericOp(*LoCopy);
1355+
constrainGenericOp(*HiCopy);
1356+
MI.eraseFromParent();
1357+
return true;
13821358
}
13831359

13841360
bool MC6809InstructionSelector::selectGeneric(MachineInstr &MI) {

‎llvm/lib/Target/MC6809/GISel/MC6809LegalizerInfo.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -46,15 +46,15 @@ MC6809LegalizerInfo::MC6809LegalizerInfo(const MC6809Subtarget &STI) : Subtarget
4646
LLT s64 = LLT::scalar(64);
4747
LLT sMax = IsHD6309 ? s32 : s16;
4848
LLT sMaxLogic = IsHD6309 ? s16 : s8;
49-
LLT sOther = IsHD6309 ? s16 : s32;
49+
// LLT sOther = IsHD6309 ? s16 : s32;
5050

5151
auto LegalTypes32 = {p, s8, s16, s32};
5252
auto LegalTypes16 = {p, s8, s16};
5353
auto LegalAccumulators16 = {s8, s16};
5454
auto LegalAccumulators8 = {s8};
5555
auto LegalAccumulators = IsHD6309 ? LegalAccumulators16 : LegalAccumulators8;
5656
auto LegalTypes = IsHD6309 ? LegalTypes32 : LegalTypes16;
57-
auto LegalTypesOther = IsHD6309 ? LegalTypes32 : LegalTypes16;
57+
// auto LegalTypesOther = IsHD6309 ? LegalTypes32 : LegalTypes16;
5858
auto LegalTypesWithOne32 = {p, s1, s8, s16, s32};
5959
auto LegalTypesWithOne16 = {p, s1, s8, s16};
6060
auto LegalTypesWithOne = IsHD6309 ? LegalTypesWithOne32 : LegalTypesWithOne16;
@@ -67,14 +67,14 @@ MC6809LegalizerInfo::MC6809LegalizerInfo(const MC6809Subtarget &STI) : Subtarget
6767
auto LegalLibcallScalars32 = {s16, s32, s64};
6868
auto LegalLibcallScalars16 = {s16, s32, s64};
6969
auto LegalLibcallScalars = IsHD6309 ? LegalLibcallScalars32 : LegalLibcallScalars16;
70-
auto NotMax32 = {s8, s16}, NotMax16 = {s8};
71-
auto NotMax = IsHD6309 ? NotMax32 : NotMax16;
72-
auto NotMin32 = {s16, s32}, NotMin16 = {s16};
73-
auto NotMin = IsHD6309 ? NotMin32 : NotMin16;
70+
// auto NotMax32 = {s8, s16}, NotMax16 = {s8};
71+
// auto NotMax = IsHD6309 ? NotMax32 : NotMax16;
72+
// auto NotMin32 = {s16, s32}, NotMin16 = {s16};
73+
// auto NotMin = IsHD6309 ? NotMin32 : NotMin16;
7474
auto NotMaxWithOne32 = {s1, s8, s16}, NotMaxWithOne16 = {s1, s8};
7575
auto NotMaxWithOne = IsHD6309 ? NotMaxWithOne32 : NotMaxWithOne16;
7676

77-
const auto IsSpecificType = [](unsigned TypeIdx, LLT Ty) { return [=](const LegalityQuery &Query) { return Query.Types[TypeIdx] == Ty; }; };
77+
// const auto IsSpecificType = [](unsigned TypeIdx, LLT Ty) { return [=](const LegalityQuery &Query) { return Query.Types[TypeIdx] == Ty; }; };
7878

7979
const auto IsScalarPointer = [](unsigned ScalarTypeIdx, unsigned PointerTypeIdx, auto Predicate) {
8080
return [=](const LegalityQuery &Query) { return Query.Types[ScalarTypeIdx].isScalar() && Query.Types[PointerTypeIdx].isPointer() && Predicate(Query.Types[ScalarTypeIdx].getSizeInBits(), Query.Types[PointerTypeIdx].getSizeInBits()); };

‎llvm/lib/Target/MC6809/GISel/MC6809RegisterBankInfo.cpp

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -230,17 +230,6 @@ const RegisterBankInfo::InstructionMapping &MC6809RegisterBankInfo::getInstrMapp
230230
LLVM_DEBUG(dbgs() << "OINQUE DEBUG " << __func__ << " : 20 : Doing getInstructionMapping() " << NumOperands << " operands\n";);
231231
return getInstructionMapping(DefaultMappingID, 1, Mapping, NumOperands);
232232
}
233-
case TargetOpcode::G_UNMERGE_VALUES: {
234-
assert(MI.getNumOperands() == 3 && "Unsupported G_UNMERGE_VALUES");
235-
unsigned Op3Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
236-
InstTy = TI.determineInstType(&MI);
237-
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
238-
&Mips::ValueMappings[Mips::GPRIdx],
239-
&Mips::ValueMappings[Mips::DPRIdx]});
240-
if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size))
241-
MappingID = CustomMappingID;
242-
break;
243-
}
244233
default:
245234
LLVM_DEBUG(dbgs() << "OINQUE DEBUG " << __func__ << " : default (nothing)\n";);
246235
break;

‎llvm/lib/Target/MC6809/MC6809CopyOpt.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,7 @@ template <typename AcceptDefT> static bool findReachingDefs(MachineInstr &MI, Sm
9090
return true;
9191
}
9292

93+
#if 0
9394
static Register findForwardedCopy(MachineInstr &MI, SmallVectorImpl<MachineInstr *> &NewSrcMIs) {
9495
Register Src = MI.getOperand(1).getReg();
9596
Register NewSrc = 0;
@@ -164,6 +165,7 @@ static bool isClobbered(MachineInstr &MI, Register NewSrc, const SmallVectorImpl
164165
}
165166
return false;
166167
}
168+
#endif
167169

168170
bool MC6809CopyOpt::runOnMachineFunction(MachineFunction &MF) {
169171
#if 0

‎llvm/lib/Target/MC6809/MC6809FrameLowering.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -311,6 +311,11 @@ uint64_t MC6809FrameLowering::staticSize(const MachineFrameInfo &MFI) const {
311311
return Size;
312312
}
313313

314+
bool MC6809FrameLowering::hasFPImpl(const MachineFunction &MF) const {
315+
const MachineFrameInfo &MFI = MF.getFrameInfo();
316+
return MFI.isFrameAddressTaken() || MFI.hasVarSizedObjects();
317+
}
318+
314319
void MC6809FrameLowering::offsetSP(MachineIRBuilder &Builder, int64_t Offset) const {
315320
assert(Offset);
316321
if (Offset < SHRT_MIN)

‎llvm/lib/Target/MC6809/MC6809FrameLowering.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ class MC6809FrameLowering : public TargetFrameLowering {
4040

4141
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
4242
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
43-
bool hasFP(const MachineFunction &MF) const override;
43+
bool hasFP(const MachineFunction &MF) const;
4444

4545
// Computes the size of the static stack.
4646
uint64_t staticSize(const MachineFrameInfo &MFI) const;
@@ -49,6 +49,8 @@ class MC6809FrameLowering : public TargetFrameLowering {
4949
bool isISR(const MachineFunction &MF) const;
5050

5151
private:
52+
bool hasFPImpl(const MachineFunction &MF) const override;
53+
5254
void offsetSP(MachineIRBuilder &Builder, int64_t Offset) const;
5355
};
5456

‎llvm/lib/Target/MC6809/MC6809InstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -718,7 +718,7 @@ void MC6809InstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicB
718718
llvm_unreachable("This process is a crock - fix me!");
719719
}
720720

721-
void MC6809InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const {
721+
void MC6809InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest, bool RenamableSrc) const {
722722
LLVM_DEBUG(dbgs() << "OINQUE DEBUG " << __func__ << " : Enter : MI = "; MI->dump(););
723723
MachineIRBuilder Builder(MBB, MI);
724724
if (DestReg == SrcReg)

‎llvm/lib/Target/MC6809/MC6809InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ class MC6809InstrInfo final : public MC6809GenInstrInfo {
106106

107107
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override;
108108

109-
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override;
109+
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false) const override;
110110

111111
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override;
112112

‎llvm/lib/Target/MC6809/MC6809TargetMachine.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212

1313
#include "MC6809TargetMachine.h"
1414

15+
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
1516
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
1617
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
1718
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
@@ -79,7 +80,8 @@ static StringRef getCPU(StringRef CPU) { return (CPU.empty() || CPU == "generic"
7980
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { return RM ? *RM : Reloc::Static; }
8081

8182
MC6809TargetMachine::MC6809TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
82-
: LLVMTargetMachine(T, MC6809DataLayout, TT, getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), SubTarget(TT, getCPU(CPU).str(), FS.str(), *this) {
83+
: CodeGenTargetMachineImpl(T, MC6809DataLayout, TT, getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM, CodeModel::Small), OL),
84+
SubTarget(TT, getCPU(CPU).str(), FS.str(), *this) {
8385
this->TLOF = std::make_unique<MC6809TargetObjectFile>();
8486

8587
initAsmInfo();

‎llvm/lib/Target/MC6809/MC6809TargetMachine.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#ifndef LLVM_MC6809_TARGET_MACHINE_H
1414
#define LLVM_MC6809_TARGET_MACHINE_H
1515

16+
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
1617
#include "llvm/IR/DataLayout.h"
1718
#include "llvm/Target/TargetMachine.h"
1819

@@ -24,7 +25,7 @@
2425
namespace llvm {
2526

2627
/// A generic MC6809 implementation.
27-
class MC6809TargetMachine : public LLVMTargetMachine {
28+
class MC6809TargetMachine : public CodeGenTargetMachineImpl {
2829
public:
2930
MC6809TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT);
3031

‎llvm/lib/Target/MC6809/MCTargetDesc/MC6809InstPrinter.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ namespace llvm {
3737
void MC6809InstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) {
3838
std::string AiryOperands;
3939
raw_string_ostream AiryOperandStream(AiryOperands);
40-
auto MnemonicInfo = getMnemonic(MI);
40+
auto MnemonicInfo = getMnemonic(*MI);
4141
assert(MnemonicInfo.second && "Missing opcode for instruction.");
4242
printInstruction(MI, Address, AiryOperandStream);
4343
AiryOperands = AiryOperandStream.str();
@@ -79,7 +79,9 @@ void MC6809InstPrinter::printRegisterList(const MCInst *MI, unsigned OpNo, raw_o
7979
}
8080
}
8181

82-
void MC6809InstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { O << getRegisterName(Reg); }
82+
void MC6809InstPrinter::printRegName(raw_ostream &O, MCRegister Reg) {
83+
O << getRegisterName(Reg);
84+
}
8385

8486
void MC6809InstPrinter::printCondCode(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
8587
const MCOperand &Op = MI->getOperand(OpNo);

‎llvm/lib/Target/MC6809/MCTargetDesc/MC6809InstPrinter.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,9 @@ class MC6809InstPrinter : public MCInstPrinter {
2828
bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
2929

3030
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override;
31-
void printRegName(raw_ostream &O, MCRegister Reg) const override;
31+
void printRegName(raw_ostream &O, MCRegister Reg) override;
3232

33-
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
33+
std::pair<const char *, uint64_t> getMnemonic(const MCInst &MI) const override;
3434

3535
// generated by TableGen
3636
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);

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