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[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (llvm#85887)
Previously we used memory like we do to move between GPRs and FPR64 with the D extension on RV32. We can instead use REG_SEQUENCE/EXTRACT_SUBREG to inform register allocation how to do the copy without memory.
1 parent 767e0c8 commit 576d81b

30 files changed

+469
-3035
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1007,7 +1007,44 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
10071007
ReplaceNode(Node, Res);
10081008
return;
10091009
}
1010+
case RISCVISD::BuildPairF64: {
1011+
if (!Subtarget->hasStdExtZdinx())
1012+
break;
1013+
1014+
assert(!Subtarget->is64Bit() && "Unexpected subtarget");
1015+
1016+
SDValue Ops[] = {
1017+
CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
1018+
Node->getOperand(0),
1019+
CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32),
1020+
Node->getOperand(1),
1021+
CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)};
1022+
1023+
SDNode *N =
1024+
CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::f64, Ops);
1025+
ReplaceNode(Node, N);
1026+
return;
1027+
}
10101028
case RISCVISD::SplitF64: {
1029+
if (Subtarget->hasStdExtZdinx()) {
1030+
assert(!Subtarget->is64Bit() && "Unexpected subtarget");
1031+
1032+
if (!SDValue(Node, 0).use_empty()) {
1033+
SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, VT,
1034+
Node->getOperand(0));
1035+
ReplaceUses(SDValue(Node, 0), Lo);
1036+
}
1037+
1038+
if (!SDValue(Node, 1).use_empty()) {
1039+
SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, VT,
1040+
Node->getOperand(0));
1041+
ReplaceUses(SDValue(Node, 1), Hi);
1042+
}
1043+
1044+
CurDAG->RemoveDeadNode(Node);
1045+
return;
1046+
}
1047+
10111048
if (!Subtarget->hasStdExtZfa())
10121049
break;
10131050
assert(Subtarget->hasStdExtD() && !Subtarget->is64Bit() &&

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -17142,9 +17142,7 @@ static MachineBasicBlock *emitReadCounterWidePseudo(MachineInstr &MI,
1714217142
static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1714317143
MachineBasicBlock *BB,
1714417144
const RISCVSubtarget &Subtarget) {
17145-
assert((MI.getOpcode() == RISCV::SplitF64Pseudo ||
17146-
MI.getOpcode() == RISCV::SplitF64Pseudo_INX) &&
17147-
"Unexpected instruction");
17145+
assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
1714817146

1714917147
MachineFunction &MF = *BB->getParent();
1715017148
DebugLoc DL = MI.getDebugLoc();
@@ -17154,9 +17152,7 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1715417152
Register HiReg = MI.getOperand(1).getReg();
1715517153
Register SrcReg = MI.getOperand(2).getReg();
1715617154

17157-
const TargetRegisterClass *SrcRC = MI.getOpcode() == RISCV::SplitF64Pseudo_INX
17158-
? &RISCV::GPRPairRegClass
17159-
: &RISCV::FPR64RegClass;
17155+
const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
1716017156
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
1716117157

1716217158
TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
@@ -17181,8 +17177,7 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1718117177
static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1718217178
MachineBasicBlock *BB,
1718317179
const RISCVSubtarget &Subtarget) {
17184-
assert((MI.getOpcode() == RISCV::BuildPairF64Pseudo ||
17185-
MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX) &&
17180+
assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
1718617181
"Unexpected instruction");
1718717182

1718817183
MachineFunction &MF = *BB->getParent();
@@ -17193,9 +17188,7 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1719317188
Register LoReg = MI.getOperand(1).getReg();
1719417189
Register HiReg = MI.getOperand(2).getReg();
1719517190

17196-
const TargetRegisterClass *DstRC =
17197-
MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPairRegClass
17198-
: &RISCV::FPR64RegClass;
17191+
const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
1719917192
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
1720017193

1720117194
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
@@ -17716,10 +17709,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1771617709
case RISCV::Select_FPR64IN32X_Using_CC_GPR:
1771717710
return emitSelectPseudo(MI, BB, Subtarget);
1771817711
case RISCV::BuildPairF64Pseudo:
17719-
case RISCV::BuildPairF64Pseudo_INX:
1772017712
return emitBuildPairF64Pseudo(MI, BB, Subtarget);
1772117713
case RISCV::SplitF64Pseudo:
17722-
case RISCV::SplitF64Pseudo_INX:
1772317714
return emitSplitF64Pseudo(MI, BB, Subtarget);
1772417715
case RISCV::PseudoQuietFLE_H:
1772517716
return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -524,20 +524,6 @@ let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
524524
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
525525
def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
526526
(PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
527-
528-
/// Pseudo-instructions needed for the soft-float ABI with RV32D
529-
530-
// Moves two GPRs to an FPR.
531-
let usesCustomInserter = 1 in
532-
def BuildPairF64Pseudo_INX
533-
: Pseudo<(outs FPR64IN32X:$dst), (ins GPR:$src1, GPR:$src2),
534-
[(set FPR64IN32X:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
535-
536-
// Moves an FPR to two GPRs.
537-
let usesCustomInserter = 1 in
538-
def SplitF64Pseudo_INX
539-
: Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64IN32X:$src),
540-
[(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64IN32X:$src))]>;
541527
} // Predicates = [HasStdExtZdinx, IsRV32]
542528

543529
let Predicates = [HasStdExtD] in {

‎llvm/test/CodeGen/RISCV/double-arith-strict.ll

Lines changed: 0 additions & 174 deletions
Original file line numberDiff line numberDiff line change
@@ -24,21 +24,7 @@ define double @fadd_d(double %a, double %b) nounwind strictfp {
2424
;
2525
; RV32IZFINXZDINX-LABEL: fadd_d:
2626
; RV32IZFINXZDINX: # %bb.0:
27-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
28-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
29-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
30-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
31-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
32-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
33-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
34-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
35-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
3627
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
37-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
38-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
39-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
40-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
41-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
4228
; RV32IZFINXZDINX-NEXT: ret
4329
;
4430
; RV64IZFINXZDINX-LABEL: fadd_d:
@@ -76,21 +62,7 @@ define double @fsub_d(double %a, double %b) nounwind strictfp {
7662
;
7763
; RV32IZFINXZDINX-LABEL: fsub_d:
7864
; RV32IZFINXZDINX: # %bb.0:
79-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
80-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
81-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
82-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
83-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
84-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
85-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
86-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
87-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
8865
; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2
89-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
90-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
91-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
92-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
93-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
9466
; RV32IZFINXZDINX-NEXT: ret
9567
;
9668
; RV64IZFINXZDINX-LABEL: fsub_d:
@@ -128,21 +100,7 @@ define double @fmul_d(double %a, double %b) nounwind strictfp {
128100
;
129101
; RV32IZFINXZDINX-LABEL: fmul_d:
130102
; RV32IZFINXZDINX: # %bb.0:
131-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
132-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
133-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
134-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
135-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
136-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
137-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
138-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
139-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
140103
; RV32IZFINXZDINX-NEXT: fmul.d a0, a0, a2
141-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
142-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
143-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
144-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
145-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
146104
; RV32IZFINXZDINX-NEXT: ret
147105
;
148106
; RV64IZFINXZDINX-LABEL: fmul_d:
@@ -180,21 +138,7 @@ define double @fdiv_d(double %a, double %b) nounwind strictfp {
180138
;
181139
; RV32IZFINXZDINX-LABEL: fdiv_d:
182140
; RV32IZFINXZDINX: # %bb.0:
183-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
184-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
185-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
186-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
187-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
188-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
189-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
190-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
191-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
192141
; RV32IZFINXZDINX-NEXT: fdiv.d a0, a0, a2
193-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
194-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
195-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
196-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
197-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
198142
; RV32IZFINXZDINX-NEXT: ret
199143
;
200144
; RV64IZFINXZDINX-LABEL: fdiv_d:
@@ -232,17 +176,7 @@ define double @fsqrt_d(double %a) nounwind strictfp {
232176
;
233177
; RV32IZFINXZDINX-LABEL: fsqrt_d:
234178
; RV32IZFINXZDINX: # %bb.0:
235-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
236-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
237-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
238-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
239-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
240179
; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
241-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
242-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
243-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
244-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
245-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
246180
; RV32IZFINXZDINX-NEXT: ret
247181
;
248182
; RV64IZFINXZDINX-LABEL: fsqrt_d:
@@ -398,25 +332,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind strictfp {
398332
;
399333
; RV32IZFINXZDINX-LABEL: fmadd_d:
400334
; RV32IZFINXZDINX: # %bb.0:
401-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
402-
; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
403-
; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
404-
; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
405-
; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
406-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
407-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
408-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
409-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
410-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
411-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
412-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
413-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
414335
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
415-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
416-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
417-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
418-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
419-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
420336
; RV32IZFINXZDINX-NEXT: ret
421337
;
422338
; RV64IZFINXZDINX-LABEL: fmadd_d:
@@ -463,27 +379,9 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
463379
;
464380
; RV32IZFINXZDINX-LABEL: fmsub_d:
465381
; RV32IZFINXZDINX: # %bb.0:
466-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
467-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
468-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
469-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
470-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
471-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
472-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
473-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
474-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
475-
; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
476-
; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
477-
; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
478-
; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
479382
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
480383
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
481384
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
482-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
483-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
484-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
485-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
486-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
487385
; RV32IZFINXZDINX-NEXT: ret
488386
;
489387
; RV64IZFINXZDINX-LABEL: fmsub_d:
@@ -572,28 +470,10 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
572470
;
573471
; RV32IZFINXZDINX-LABEL: fnmadd_d:
574472
; RV32IZFINXZDINX: # %bb.0:
575-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
576-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
577-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
578-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
579-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
580-
; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
581-
; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
582-
; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
583-
; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
584-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
585-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
586-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
587-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
588473
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
589474
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
590475
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
591476
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
592-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
593-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
594-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
595-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
596-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
597477
; RV32IZFINXZDINX-NEXT: ret
598478
;
599479
; RV64IZFINXZDINX-LABEL: fnmadd_d:
@@ -701,28 +581,10 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
701581
;
702582
; RV32IZFINXZDINX-LABEL: fnmadd_d_2:
703583
; RV32IZFINXZDINX: # %bb.0:
704-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
705-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
706-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
707-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
708-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
709-
; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
710-
; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
711-
; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
712-
; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
713-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
714-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
715-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
716-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
717584
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
718585
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
719586
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
720587
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a2, a0, a4
721-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
722-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
723-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
724-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
725-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
726588
; RV32IZFINXZDINX-NEXT: ret
727589
;
728590
; RV64IZFINXZDINX-LABEL: fnmadd_d_2:
@@ -829,27 +691,9 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp {
829691
;
830692
; RV32IZFINXZDINX-LABEL: fnmsub_d:
831693
; RV32IZFINXZDINX: # %bb.0:
832-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
833-
; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
834-
; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
835-
; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
836-
; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
837-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
838-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
839-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
840-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
841-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
842-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
843-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
844-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
845694
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
846695
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
847696
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
848-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
849-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
850-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
851-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
852-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
853697
; RV32IZFINXZDINX-NEXT: ret
854698
;
855699
; RV64IZFINXZDINX-LABEL: fnmsub_d:
@@ -932,27 +776,9 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
932776
;
933777
; RV32IZFINXZDINX-LABEL: fnmsub_d_2:
934778
; RV32IZFINXZDINX: # %bb.0:
935-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
936-
; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
937-
; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
938-
; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
939-
; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
940-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
941-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
942-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
943-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
944-
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
945-
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
946-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
947-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
948779
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
949780
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
950781
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a2, a0, a4
951-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
952-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
953-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
954-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
955-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
956782
; RV32IZFINXZDINX-NEXT: ret
957783
;
958784
; RV64IZFINXZDINX-LABEL: fnmsub_d_2:

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