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Yeting Kuomylai-mtk
Yeting Kuo
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[RISCV] Avoid using x7/t2 for indirect branches which need landing pad.
When Zicfilp enabled, this avoids selecting brind to PseudoBRIND, since PseudoBRIND may uses X7 as rs1 and be identified as a software guarded jump. There is an another PR llvm#66762 to use software guarded jump for jumptable branch.
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llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -116,6 +116,9 @@ def FeatureStdExtZicfilp
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def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
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AssemblerPredicate<(all_of FeatureStdExtZicfilp),
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"'Zicfilp' (Landing pad)">;
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def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
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AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>;
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def FeatureStdExtZicfiss
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: SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",

llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -1450,16 +1450,27 @@ let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
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def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12:$imm12), []>,
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PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
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let Predicates = [HasStdExtZicfilp] in {
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let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
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let Predicates = [HasStdExtZicfilp],
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isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in {
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def PseudoBRINDX7 : Pseudo<(outs), (ins GPRX7:$rs1, simm12:$imm12), []>,
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PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
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def PseudoBRINDNonX7 : Pseudo<(outs), (ins GPRJALRNonX7:$rs1, simm12:$imm12), []>,
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PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
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}
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// For Zicfilp, need to avoid using X7/T2 for indirect branches which need
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// landing pad.
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let Predicates = [HasStdExtZicfilp] in {
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def : Pat<(brind GPRJALRNonX7:$rs1), (PseudoBRINDNonX7 GPRJALRNonX7:$rs1, 0)>;
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def : Pat<(brind (add GPRJALRNonX7:$rs1, simm12:$imm12)),
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(PseudoBRINDNonX7 GPRJALRNonX7:$rs1, simm12:$imm12)>;
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}
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let Predicates = [NoStdExtZicfilp] in {
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def : Pat<(brind GPRJALR:$rs1), (PseudoBRIND GPRJALR:$rs1, 0)>;
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def : Pat<(brind (add GPRJALR:$rs1, simm12:$imm12)),
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(PseudoBRIND GPRJALR:$rs1, simm12:$imm12)>;
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}
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// PseudoCALLReg is a generic pseudo instruction for calls which will eventually
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// expand to auipc and jalr while encoding, with any given register used as the

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

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@@ -157,6 +157,8 @@ def GPRX7 : GPRRegisterClass<(add X7)>;
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// by tablegen.
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def GPRJALR : GPRRegisterClass<(sub GPR, (sequence "X%u", 0, 5))>;
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def GPRJALRNonX7 : GPRRegisterClass<(sub GPRJALR, X7)>;
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def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
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(sequence "X%u", 8, 9))>;
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@@ -0,0 +1,49 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -stop-after=finalize-isel < %s | FileCheck -check-prefixes=ZICFILP %s
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@foo.arr = internal unnamed_addr constant [2 x ptr] [ptr blockaddress(@foo, %5), ptr blockaddress(@foo, %8)], align 8
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@x = dso_local global i32 0, align 4
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define void @foo(i32 noundef signext %0) {
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; CHECK: PseudoBRIND killed [[VAR:%.*]], 0
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; ZICFILP: PseudoBRINDNonX7 killed [[VAR:%.*]], 0
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%2 = sext i32 %0 to i64
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%3 = getelementptr inbounds [2 x ptr], ptr @foo.arr, i64 0, i64 %2
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%4 = load ptr, ptr %3, align 8
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indirectbr ptr %4, [label %5, label %8]
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5: ; preds = %1
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%6 = load i32, ptr @x, align 4
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%7 = add nsw i32 %6, 2
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store i32 %7, ptr @x, align 4
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br label %8
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8: ; preds = %5, %1
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%9 = load i32, ptr @x, align 4
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%10 = add nsw i32 %9, 1
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store i32 %10, ptr @x, align 4
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ret void
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}
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define void @bar(i32 noundef signext %0) {
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; CHECK: PseudoBRIND killed [[VAR:%.*]], 4
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; ZICFILP: PseudoBRINDNonX7 killed [[VAR:%.*]], 4
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%2 = sext i32 %0 to i64
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%3 = getelementptr inbounds [2 x ptr], ptr @foo.arr, i64 0, i64 %2
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%4 = load ptr, ptr %3, align 8
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%t = getelementptr inbounds i8, ptr @foo.arr, i64 4
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indirectbr ptr %t, [label %5, label %8]
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5: ; preds = %1
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%6 = load i32, ptr @x, align 4
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%7 = add nsw i32 %6, 2
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store i32 %7, ptr @x, align 4
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br label %8
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8: ; preds = %5, %1
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%9 = load i32, ptr @x, align 4
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%10 = add nsw i32 %9, 1
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store i32 %10, ptr @x, align 4
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ret void
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}

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