FPGA: Update seeds of the GZIP and QRD design to meet performance target (#1414)

Author: yuguen

DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt

@@ -74,10 +74,10 @@ elseif(DEVICE_FLAG MATCHES "S10")
     # S10 parameters
     set(NUM_ENGINES 2)
     if(DEFINED LOW_LATENCY)
-        set(SEED "-Xsseed=16")
+        set(SEED "-Xsseed=2")
         set(NUM_REORDER "")
     else()
-        set(SEED "-Xsseed=1")
+        set(SEED "-Xsseed=10")
         # For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR.
         # For Low Latency variant this is not necessary since only one channel of global memory is used (host memory).
         set(NUM_REORDER "-Xsnum-reorder=6")

DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt

@@ -64,15 +64,15 @@ if(DEVICE_FLAG MATCHES "A10")
     set(COMPLEX 1)
     set(FIXED_ITERATIONS 64)
     set(CLOCK_TARGET "-Xsclock=360MHz")
-    set(SEED "-Xsseed=7")
+    set(SEED "-Xsseed=1")
 elseif(DEVICE_FLAG MATCHES "S10")
     # S10 parameters
     set(ROWS_COMPONENT 256)
     set(COLS_COMPONENT 256)
     set(COMPLEX 1)
     set(FIXED_ITERATIONS 110)
     set(CLOCK_TARGET "-Xsclock=480MHz")
-    set(SEED "-Xsseed=2")
+    set(SEED "-Xsseed=3")
 elseif(DEVICE_FLAG MATCHES "Agilex")
     # Agilex™ parameters
     set(ROWS_COMPONENT 256)