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FPGA: replace Agilex™ with Agilex® (#1372)
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‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/README.md

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@@ -37,7 +37,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -151,7 +151,7 @@ The design uses the following generic header files.
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### On Linux*
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1. Change to the sample directory.
154-
2. Configure the build system for the Agilex™ device family, which is the default.
154+
2. Configure the build system for the Agilex® device family, which is the default.
155155

156156
```
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mkdir build
@@ -195,7 +195,7 @@ The design uses the following generic header files.
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### On Windows*
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197197
1. Change to the sample directory.
198-
2. Configure the build system for the Agilex™ device family, which is the default.
198+
2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/README.md

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@@ -40,7 +40,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -122,7 +122,7 @@ Performance results are based on testing as of Jan 31, 2022.
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### On Linux*
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1. Change to the sample directory.
125-
2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
126126

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```
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mkdir build
@@ -162,7 +162,7 @@ Performance results are based on testing as of Jan 31, 2022.
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### On Windows*
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1. Change to the sample directory.
165-
2. Configure the build system for the Agilex™ device family, which is the default.
165+
2. Configure the build system for the Agilex® device family, which is the default.
166166
```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/README.md

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@@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
47-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -143,7 +143,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and `
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### On Linux*
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145145
1. Change to the sample directory.
146-
2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
149149
mkdir build
@@ -187,7 +187,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and `
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### On Windows*
188188
189189
1. Change to the sample directory.
190-
2. Configure the build system for the Agilex™ device family, which is the default.
190+
2. Configure the build system for the Agilex® device family, which is the default.
191191
```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/README.md

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@@ -57,7 +57,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
60-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -165,7 +165,7 @@ Additionaly, the cmake build system can be configured using the following parame
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
169169

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```
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mkdir build
@@ -209,7 +209,7 @@ Additionaly, the cmake build system can be configured using the following parame
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/README.md

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@@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
42-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -153,7 +153,7 @@ This design measures the FPGA performance to determine how many assets can be pr
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### On Linux*
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155155
1. Change to the sample directory.
156-
2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
157157

158158
```
159159
mkdir build
@@ -193,7 +193,7 @@ This design measures the FPGA performance to determine how many assets can be pr
193193
### On Windows*
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1. Change to the sample directory.
196-
2. Configure the build system for the Agilex™ device family, which is the default.
196+
2. Configure the build system for the Agilex® device family, which is the default.
197197
```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/README.md

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@@ -40,7 +40,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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--- |---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
43-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
43+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
4444
| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -146,7 +146,7 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d
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### On Linux*
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1. Change to the sample directory.
149-
2. Configure the build system for the default target (the Agilex™ device family).
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2. Configure the build system for the default target (the Agilex® device family).
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```
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mkdir build
152152
cd build
@@ -195,7 +195,7 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d
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### On Windows*
196196
197197
1. Change to the sample directory.
198-
2. Configure the build system for the default target (the Agilex™ device family).
198+
2. Configure the build system for the default target (the Agilex® device family).
199199
```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/README.md

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@@ -36,7 +36,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
39-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
39+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
4141

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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -304,7 +304,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl
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### On Linux*
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306306
1. Change to the sample directory.
307-
2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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309309
```
310310
mkdir build
@@ -354,7 +354,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl
354354
### On Windows*
355355
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1. Change to the sample directory.
357-
2. Configure the build system for the Agilex™ device family, which is the default.
357+
2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/README.md

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@@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
42-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
42+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
4343
| Software | Intel® oneAPI DPC++/C++ Compiler
4444

4545
> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -57,7 +57,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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The GZIP DEFLATE algorithm uses a GZIP-compatible Limpel-Ziv 77 (LZ77) algorithm for data de-duplication and a GZIP-compatible Static Huffman algorithm for bit reduction. The implementation includes three FPGA accelerated tasks (LZ77, Static Huffman, and CRC).
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The FPGA implementation of the algorithm enables either one or two independent GZIP compute engines to operate in parallel on the FPGA. The available FPGA resources constrain the number of engines. By default, the design is parameterized to create a single engine when the design is compiled to target an Intel® Arria® 10 FPGA. Two engines are created when compiling for Intel® Stratix® 10 or Agilex™ FPGAs, which are a larger device.
60+
The FPGA implementation of the algorithm enables either one or two independent GZIP compute engines to operate in parallel on the FPGA. The available FPGA resources constrain the number of engines. By default, the design is parameterized to create a single engine when the design is compiled to target an Intel® Arria® 10 FPGA. Two engines are created when compiling for Intel® Stratix® 10 or Agilex® FPGAs, which are a larger device.
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This reference design contains two variants: "High Bandwidth" and "Low-Latency."
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### On Linux*
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144144
1. Change to the sample directory.
145-
2. Configure the build system for the Agilex™ device family, which is the default.
145+
2. Configure the build system for the Agilex® device family, which is the default.
146146

147147
```
148148
mkdir build
@@ -189,7 +189,7 @@ Performance results are based on testing as of October 27, 2020.
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### On Windows*
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1. Change to the sample directory.
192-
2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
193193
```
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mkdir build
195195
cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/README.md

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| Optimized for | Description
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|:--- |:---
4343
| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15
44-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
44+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
4545
| Software | Intel® oneAPI DPC++/C++ Compiler
4646

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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -118,7 +118,7 @@ For `constexpr_math.hpp`, `pipe_utils.hpp`, and `unrolled_loop.hpp` see the READ
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/README.md

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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
52-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
52+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
5353
| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -121,7 +121,7 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl
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### On Linux*
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123123
1. Change to the sample directory.
124-
2. Configure the build system for the Agilex™ device family, which is the default.
124+
2. Configure the build system for the Agilex® device family, which is the default.
125125

126126
```
127127
mkdir build
@@ -165,7 +165,7 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl
165165
### On Windows*
166166
167167
1. Change to the sample directory.
168-
2. Configure the build system for the Agilex™ device family, which is the default.
168+
2. Configure the build system for the Agilex® device family, which is the default.
169169
```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/README.md

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@@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
4646
| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
47-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
47+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
4848
| Software | Intel® oneAPI DPC++/C++ Compiler
4949

5050
> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -76,7 +76,7 @@ The QR decomposition algorithm factors a complex _m_ × _n_ matrix, where _m_
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With this optimization, our FPGA implementation requires 4*m* DSPs to compute the complex floating point dot product or 2*m* DSPs for the real case. The matrix size is constrained by the total FPGA DSP resources available.
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By default, the design is parameterized to process 128 × 128 matrices when compiled targeting an Intel® Arria® 10 FPGA. It is parameterized to process 256 × 256 matrices when compiled targeting a Intel® Stratix® 10 or Intel® Agilex™ FPGA; however, the design can process matrices from 4 x 4 to 512 x 512.
79+
By default, the design is parameterized to process 128 × 128 matrices when compiled targeting an Intel® Arria® 10 FPGA. It is parameterized to process 256 × 256 matrices when compiled targeting a Intel® Stratix® 10 or Intel® Agilex® FPGA; however, the design can process matrices from 4 x 4 to 512 x 512.
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To optimize the performance-critical loop in its algorithm, the design leverages concepts discussed in the following FPGA tutorials:
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@@ -133,7 +133,7 @@ Additionaly, the cmake build system can be configured using the following parame
133133
### On Linux*
134134

135135
1. Change to the sample directory.
136-
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136+
2. Configure the build system for the Agilex® device family, which is the default.
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138138
```
139139
mkdir build
@@ -177,7 +177,7 @@ Additionaly, the cmake build system can be configured using the following parame
177177
### On Windows*
178178
179179
1. Change to the sample directory.
180-
2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/README.md

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@@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
47-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
47+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
4848
| Software | Intel® oneAPI DPC++/C++ Compiler
4949

5050
> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -123,7 +123,7 @@ Additionaly, the cmake build system can be configured using the following parame
123123
### On Linux*
124124

125125
1. Change to the sample directory.
126-
2. Configure the build system for the Agilex™ device family, which is the default.
126+
2. Configure the build system for the Agilex® device family, which is the default.
127127

128128
```
129129
mkdir build
@@ -166,7 +166,7 @@ Additionaly, the cmake build system can be configured using the following parame
166166
### On Windows*
167167
168168
1. Change to the sample directory.
169-
2. Configure the build system for the Agilex™ device family, which is the default.
169+
2. Configure the build system for the Agilex® device family, which is the default.
170170
```
171171
mkdir build
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cd build

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