Document a few more ID register bits. This should add most of the stuff

in ARMv8.5 as far as the ISAR and PFR registers are concerned.

ok deraadt@

Author: kettenis

sys/arch/arm64/include/armreg.h

@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.23 2022/11/08 14:01:13 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.24 2022/11/24 14:36:07 kettenis Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -476,7 +476,7 @@
 #define	 ID_AA64MMFR1_XNX_IMPL		(0x1 << ID_AA64MMFR1_XNX_SHIFT)
 
 /* ID_AA64PFR0_EL1 */
-#define	ID_AA64PFR0_MASK		0xff0000000fffffffULL
+#define	ID_AA64PFR0_MASK		0xff0fffffffffffffULL
 #define	ID_AA64PFR0_EL0_SHIFT		0
 #define	ID_AA64PFR0_EL0_MASK		(0xf << ID_AA64PFR0_EL0_SHIFT)
 #define	ID_AA64PFR0_EL0(x)		((x) & ID_AA64PFR0_EL0_MASK)
@@ -515,6 +515,32 @@
 #define	ID_AA64PFR0_GIC(x)		((x) & ID_AA64PFR0_GIC_MASK)
 #define	 ID_AA64PFR0_GIC_CPUIF_NONE	(0x0 << ID_AA64PFR0_GIC_SHIFT)
 #define	 ID_AA64PFR0_GIC_CPUIF_EN	(0x1 << ID_AA64PFR0_GIC_SHIFT)
+#define	ID_AA64PFR0_RAS_SHIFT		28
+#define	ID_AA64PFR0_RAS_MASK		(0xfULL << ID_AA64PFR0_RAS_SHIFT)
+#define	ID_AA64PFR0_RAS(x)		((x) & ID_AA64PFR0_RAS_MASK)
+#define	 ID_AA64PFR0_RAS_NONE		(0x0ULL << ID_AA64PFR0_RAS_SHIFT)
+#define	 ID_AA64PFR0_RAS_IMPL		(0x1ULL << ID_AA64PFR0_RAS_SHIFT)
+#define	 ID_AA64PFR0_RAS_IMPL_V1P1	(0x2ULL << ID_AA64PFR0_RAS_SHIFT)
+#define	ID_AA64PFR0_SVE_SHIFT		32
+#define	ID_AA64PFR0_SVE_MASK		(0xfULL << ID_AA64PFR0_SVE_SHIFT)
+#define	ID_AA64PFR0_SVE(x)		((x) & ID_AA64PFR0_SVE_MASK)
+#define	 ID_AA64PFR0_SVE_NONE		(0x0ULL << ID_AA64PFR0_SVE_SHIFT)
+#define	 ID_AA64PFR0_SVE_IMPL		(0x1ULL << ID_AA64PFR0_SVE_SHIFT)
+#define	ID_AA64PFR0_SEL2_SHIFT		36
+#define	ID_AA64PFR0_SEL2_MASK		(0xfULL << ID_AA64PFR0_SEL2_SHIFT)
+#define	ID_AA64PFR0_SEL2(x)		((x) & ID_AA64PFR0_SEL2_MASK)
+#define	 ID_AA64PFR0_SEL2_NONE		(0x0ULL << ID_AA64PFR0_SEL2_SHIFT)
+#define	 ID_AA64PFR0_SEL2_IMPL		(0x1ULL << ID_AA64PFR0_SEL2_SHIFT)
+#define	ID_AA64PFR0_MPAM_SHIFT		40
+#define	ID_AA64PFR0_MPAM_MASK		(0xfULL << ID_AA64PFR0_MPAM_SHIFT)
+#define	ID_AA64PFR0_MPAM(x)		((x) & ID_AA64PFR0_MPAM_MASK)
+#define	 ID_AA64PFR0_MPAM_NONE		(0x0ULL << ID_AA64PFR0_MPAM_SHIFT)
+#define	 ID_AA64PFR0_MPAM_IMPL		(0x1ULL << ID_AA64PFR0_MPAM_SHIFT)
+#define	ID_AA64PFR0_AMU_SHIFT		44
+#define	ID_AA64PFR0_AMU_MASK		(0xfULL << ID_AA64PFR0_AMU_SHIFT)
+#define	ID_AA64PFR0_AMU(x)		((x) & ID_AA64PFR0_AMU_MASK)
+#define	 ID_AA64PFR0_AMU_NONE		(0x0ULL << ID_AA64PFR0_AMU_SHIFT)
+#define	 ID_AA64PFR0_AMU_IMPL		(0x1ULL << ID_AA64PFR0_AMU_SHIFT)
 #define	ID_AA64PFR0_DIT_SHIFT		48
 #define	ID_AA64PFR0_DIT_MASK		(0xfULL << ID_AA64PFR0_DIT_SHIFT)
 #define	ID_AA64PFR0_DIT(x)		((x) & ID_AA64PFR0_DIT_MASK)
@@ -532,6 +558,30 @@
 #define	 ID_AA64PFR0_CSV3_UNKNOWN	(0x0ULL << ID_AA64PFR0_CSV3_SHIFT)
 #define	 ID_AA64PFR0_CSV3_IMPL		(0x1ULL << ID_AA64PFR0_CSV3_SHIFT)
 
+/* ID_AA64PFR1_EL1 */
+#define	ID_AA64PFR1_MASK		0x000000000000ffffULL
+#define	ID_AA64PFR1_BT_SHIFT		0
+#define	ID_AA64PFR1_BT_MASK		(0xf << ID_AA64PFR1_BT_SHIFT)
+#define	ID_AA64PFR1_BT(x)		((x) & ID_AA64PFR1_BT_MASK)
+#define	 ID_AA64PFR1_BT_NONE		(0 << ID_AA64PFR1_BT_SHIFT)
+#define	 ID_AA64PFR1_BT_IMPL		(1 << ID_AA64PFR1_BT_SHIFT)
+#define	ID_AA64PFR1_SBSS_SHIFT		4
+#define	ID_AA64PFR1_SBSS_MASK		(0xf << ID_AA64PFR1_SBSS_SHIFT)
+#define	ID_AA64PFR1_SBSS(x)		((x) & ID_AA64PFR1_SBSS_MASK)
+#define	 ID_AA64PFR1_SBSS_NONE		(0 << ID_AA64PFR1_SBSS_SHIFT)
+#define	 ID_AA64PFR1_SBSS_PSTATE	(1 << ID_AA64PFR1_SBSS_SHIFT)
+#define	 ID_AA64PFR1_SBSS_PSTATE_MSR	(2 << ID_AA64PFR1_SBSS_SHIFT)
+#define	ID_AA64PFR1_MTE_SHIFT		8
+#define	ID_AA64PFR1_MTE_MASK		(0xf << ID_AA64PFR1_MTE_SHIFT)
+#define	ID_AA64PFR1_MTE(x)		((x) & ID_AA64PFR1_MTE_MASK)
+#define	 ID_AA64PFR1_MTE_NONE		(0 << ID_AA64PFR1_MTE_SHIFT)
+#define	 ID_AA64PFR1_MTE_IMPL		(1 << ID_AA64PFR1_MTE_SHIFT)
+#define	ID_AA64PFR1_RAS_FRAC_SHIFT	12
+#define	ID_AA64PFR1_RAS_FRAC_MASK	(0xf << ID_AA64PFR1_RAS_FRAC_SHIFT)
+#define	ID_AA64PFR1_RAS_FRAC(x)		((x) & ID_AA64PFR1_RAS_FRAC_MASK)
+#define	 ID_AA64PFR1_RAS_FRAC_NONE	(0 << ID_AA64PFR1_RAS_FRAC_SHIFT)
+#define	 ID_AA64PFR1_RAS_FRAC_IMPL	(1 << ID_AA64PFR1_RAS_FRAC_SHIFT)
+
 /* MAIR_EL1 - Memory Attribute Indirection Register */
 #define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))
 #define	MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))