Skip to content

Commit be689f1

Browse files
committed
use the new CPU_ID_AA64ISAR0 sysctl to determine CPU features on arm64
ok tb@, deraadt@, kettenis@
1 parent 49f7164 commit be689f1

File tree

1 file changed

+55
-5
lines changed

1 file changed

+55
-5
lines changed

lib/libcrypto/arch/aarch64/arm64cap.c

Lines changed: 55 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,68 @@
1-
/* $OpenBSD: arm64cap.c,v 1.1 2022/03/23 15:13:31 tb Exp $ */
1+
/* $OpenBSD: arm64cap.c,v 1.2 2022/03/25 17:42:07 robert Exp $ */
22
#include <stdio.h>
33
#include <stdlib.h>
44
#include <string.h>
55
#include <setjmp.h>
66
#include <signal.h>
77
#include <openssl/crypto.h>
88

9+
#if defined(__OpenBSD__)
10+
#include <sys/sysctl.h>
11+
#include <machine/cpu.h> /* CPU_ID_AA64ISAR0 */
12+
#endif
13+
914
#include "arm64_arch.h"
1015

16+
/* ID_AA64ISAR0_EL1 required for OPENSSL_cpuid_setup */
17+
#define ID_AA64ISAR0_AES_SHIFT 4
18+
#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT)
19+
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
20+
#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT)
21+
#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT)
22+
#define ID_AA64ISAR0_SHA1_SHIFT 8
23+
#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT)
24+
#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK)
25+
#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT)
26+
#define ID_AA64ISAR0_SHA2_SHIFT 12
27+
#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT)
28+
#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
29+
#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT)
30+
1131
unsigned int OPENSSL_armcap_P;
1232

33+
#if defined(__GNUC__) && __GNUC__ >= 2
34+
void OPENSSL_cpuid_setup(void) __attribute__((constructor));
35+
#endif
36+
37+
#if defined(CPU_ID_AA64ISAR0)
38+
void
39+
OPENSSL_cpuid_setup(void)
40+
{
41+
int isar0_mib[] = { CTL_MACHDEP, CPU_ID_AA64ISAR0 };
42+
size_t len = sizeof(uint64_t);
43+
uint64_t cpu_id = 0;
44+
45+
if (OPENSSL_armcap_P != 0)
46+
return;
47+
48+
if (sysctl(isar0_mib, 2, &cpu_id, &len, NULL, 0) < 0)
49+
return;
50+
51+
OPENSSL_armcap_P |= ARMV7_NEON;
52+
53+
if (ID_AA64ISAR0_AES(cpu_id) >= ID_AA64ISAR0_AES_BASE)
54+
OPENSSL_armcap_P |= ARMV8_AES;
55+
56+
if (ID_AA64ISAR0_AES(cpu_id) >= ID_AA64ISAR0_AES_PMULL)
57+
OPENSSL_armcap_P |= ARMV8_PMULL;
58+
59+
if (ID_AA64ISAR0_SHA1(cpu_id) >= ID_AA64ISAR0_SHA1_BASE)
60+
OPENSSL_armcap_P |= ARMV8_SHA1;
61+
62+
if (ID_AA64ISAR0_SHA2(cpu_id) >= ID_AA64ISAR0_SHA2_BASE)
63+
OPENSSL_armcap_P |= ARMV8_SHA256;
64+
}
65+
#else
1366
#if __ARM_ARCH__ >= 7
1467
static sigset_t all_masked;
1568

@@ -28,10 +81,6 @@ void _armv8_sha256_probe(void);
2881
void _armv8_pmull_probe(void);
2982
#endif
3083

31-
#if defined(__GNUC__) && __GNUC__>=2
32-
void OPENSSL_cpuid_setup(void) __attribute__((constructor));
33-
#endif
34-
3584
void
3685
OPENSSL_cpuid_setup(void)
3786
{
@@ -86,3 +135,4 @@ OPENSSL_cpuid_setup(void)
86135
sigprocmask(SIG_SETMASK, &oset, NULL);
87136
#endif
88137
}
138+
#endif

0 commit comments

Comments
 (0)