Compare float/double using VFP registers

Here We need `extern "C"` to generate `aapcs` or `aapcs-vfp` calls
depending on target configuration.

Doing this LLVM generate:

00005614 <nesf2vfp>:
    5614:	eeb40ae0 	vcmpe.f32	s0, s1
    5618:	e3a00000 	mov	r0, #0
    561c:	eef1fa10 	vmrs	APSR_nzcv, fpscr
    5620:	13000001 	movwne	r0, rust-lang#1
    5624:	e12fff1e 	bx	lr

That's exactly what We need

Author: paoloteti

README.md

@@ -111,14 +111,14 @@ features = ["c"]
 - [ ] arm/floatsisfvfp.S
 - [ ] arm/floatunssidfvfp.S
 - [ ] arm/floatunssisfvfp.S
-- [ ] arm/gedf2vfp.S
-- [ ] arm/gesf2vfp.S
-- [ ] arm/gtdf2vfp.S
-- [ ] arm/gtsf2vfp.S
-- [ ] arm/ledf2vfp.S
-- [ ] arm/lesf2vfp.S
-- [ ] arm/ltdf2vfp.S
-- [ ] arm/ltsf2vfp.S
+- [x] arm/gedf2vfp.S
+- [x] arm/gesf2vfp.S
+- [x] arm/gtdf2vfp.S
+- [x] arm/gtsf2vfp.S
+- [x] arm/ledf2vfp.S
+- [x] arm/lesf2vfp.S
+- [x] arm/ltdf2vfp.S
+- [x] arm/ltsf2vfp.S
 - [ ] arm/modsi3.S (generic version is done)
 - [x] arm/muldf3vfp.S
 - [x] arm/mulsf3vfp.S

src/float/cmp.rs

@@ -212,4 +212,44 @@ intrinsics! {
     pub extern "aapcs" fn __aeabi_dcmpgt(a: f64, b: f64) -> i32 {
         (__gtdf2(a, b) > 0) as i32
     }
+
+    pub extern "C" fn __gesf2vfp(a: f32, b: f32) -> i32 {
+        (a >= b) as i32
+    }
+
+    pub extern "C" fn __gedf2vfp(a: f64, b: f64) -> i32 {
+        (a >= b) as i32
+    }
+
+    pub extern "C" fn __gtdf2vfp(a: f32, b: f32) -> i32 {
+        (a > b) as i32
+    }
+
+    pub extern "C" fn __gtdd2vfp(a: f64, b: f64) -> i32 {
+        (a > b) as i32
+    }
+
+    pub extern "C" fn __ledf2vfp(a: f32, b: f32) -> i32 {
+        (a <= b) as i32
+    }
+
+    pub extern "C" fn __ledd2vfp(a: f64, b: f64) -> i32 {
+        (a <= b) as i32
+    }
+
+    pub extern "C" fn __ltdf2vfp(a: f32, b: f32) -> i32 {
+        (a < b) as i32
+    }
+
+    pub extern "C" fn __ltdd2vfp(a: f64, b: f64) -> i32 {
+        (a < b) as i32
+    }
+
+    pub extern "C" fn __nesf2vfp(a: f32, b: f32) -> i32 {
+        (a != b) as i32
+    }
+
+    pub extern "C" fn __nedf2vfp(a: f64, b: f64) -> i32 {
+        (a != b) as i32
+    }
 }

testcrate/build.rs

@@ -143,6 +143,108 @@ fn main() {
         },
         "compiler_builtins::float::cmp::__lesf2(a, b)");
 
+    if target_arch_arm {
+        gen(|(a, b): (MyF32, MyF32)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 != b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__nesf2vfp(a, b)");
+
+        gen(|(a, b): (MyF64, MyF64)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 != b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__nedf2vfp(a, b)");
+
+        gen(|(a, b): (MyF32, MyF32)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 < b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__ltdf2vfp(a, b)");
+
+        gen(|(a, b): (MyF64, MyF64)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 < b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__ltdd2vfp(a, b)");
+
+        gen(|(a, b): (MyF32, MyF32)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 <= b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__ledf2vfp(a, b)");
+
+        gen(|(a, b): (MyF64, MyF64)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 <= b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__ledd2vfp(a, b)");
+
+        gen(|(a, b): (MyF32, MyF32)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 > b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__gtdf2vfp(a, b)");
+
+        gen(|(a, b): (MyF64, MyF64)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 > b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__gtdd2vfp(a, b)");
+
+        gen(|(a, b): (MyF32, MyF32)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 >= b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__gesf2vfp(a, b)");
+
+        gen(|(a, b): (MyF64, MyF64)| {
+                if a.0.is_nan() || b.0.is_nan() {
+                    None
+                } else {
+                    let c = (a.0 >= b.0) as i32;
+                    Some(c)
+                }
+            },
+            "compiler_builtins::float::cmp::__gedf2vfp(a, b)");
+    }
+
     // float/conv.rs
     gen(|a: MyF64| i64(a.0).ok(),
         "compiler_builtins::float::conv::__fixdfdi(a)");