Merge #106

106: Stir register and debugger check r=adamgreig a=thenewwazoo

Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached.

Co-authored-by: Brandon Matthews <[email protected]>
Co-authored-by: Brandon Matthews <[email protected]>

Author: 3 people

src/peripheral/dcb.rs

@@ -2,6 +2,7 @@
 
 use volatile_register::{RW, WO};
 
+use core::ptr;
 use peripheral::DCB;
 
 const DCB_DEMCR_TRCENA: u32 = 1 << 24;
@@ -20,18 +21,37 @@ pub struct RegisterBlock {
 }
 
 impl DCB {
-    /// Enables TRACE. This is for example required by the 
+    /// Enables TRACE. This is for example required by the
     /// `peripheral::DWT` cycle counter to work properly.
     /// As by STM documentation, this flag is not reset on
     /// soft-reset, only on power reset.
     pub fn enable_trace(&mut self) {
         // set bit 24 / TRCENA
-        unsafe { self.demcr.modify(|w| w | DCB_DEMCR_TRCENA); }
+        unsafe {
+            self.demcr.modify(|w| w | DCB_DEMCR_TRCENA);
+        }
     }
-    
+
     /// Disables TRACE. See `DCB::enable_trace()` for more details
     pub fn disable_trace(&mut self) {
         // unset bit 24 / TRCENA
-        unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); }
+        unsafe {
+            self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA);
+        }
+    }
+
+    /// Is there a debugger attached? (see note)
+    ///
+    /// Note: This function is [reported not to
+    /// work](http://web.archive.org/web/20180821191012/https://community.nxp.com/thread/424925#comment-782843)
+    /// on Cortex-M0 devices. Per the ARM v6-M Architecture Reference Manual, "Access to the DHCSR
+    /// from software running on the processor is IMPLEMENTATION DEFINED". Indeed, from the
+    /// [Cortex-M0+ r0p1 Technical Reference Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0484c/BABJHEIG.html), "Note Software cannot access the debug registers."
+    pub fn is_debugger_attached() -> bool {
+        unsafe {
+            // do an 8-bit read of the 32-bit DHCSR register, and get the LSB
+            let value = ptr::read_volatile(Self::ptr() as *const u8);
+            value & 0x1 == 1
+        }
     }
 }

src/peripheral/nvic.rs

@@ -1,7 +1,7 @@
 //! Nested Vector Interrupt Controller
 
 #[cfg(not(armv6m))]
-use volatile_register::RO;
+use volatile_register::{RO, WO};
 use volatile_register::RW;
 
 use interrupt::Nr;
@@ -65,9 +65,38 @@ pub struct RegisterBlock {
     /// so convenient byte-sized representation wouldn't work on that
     /// architecture.
     pub ipr: [RW<u32>; 8],
+
+    #[cfg(not(armv6m))]
+    reserved5: [u32; 208],
+
+    #[cfg(armv6m)]
+    reserved5: [u32; 696],
+
+    #[cfg(not(armv6m))]
+    /// Software Trigger Interrupt
+    pub stir: WO<u32>,
 }
 
 impl NVIC {
+    #[cfg(not(armv6m))]
+    /// Request an IRQ in software
+    ///
+    /// Writing a value to the INTID field is the same as manually pending an interrupt by setting
+    /// the corresponding interrupt bit in an Interrupt Set Pending Register. This is similar to
+    /// `set_pending`.
+    ///
+    /// This method is not available on ARMv6-M chips.
+    pub fn request<I>(&mut self, interrupt: I)
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+
+        unsafe {
+            self.stir.write(nr as u32);
+        }
+    }
+
     /// Clears `interrupt`'s pending state
     #[deprecated(since = "0.5.8", note = "Use `NVIC::unpend`")]
     pub fn clear_pending<I>(&mut self, interrupt: I)

src/peripheral/test.rs

@@ -109,6 +109,8 @@ fn nvic() {
     assert_eq!(address(&nvic.icpr), 0xE000E280);
     assert_eq!(address(&nvic.iabr), 0xE000E300);
     assert_eq!(address(&nvic.ipr), 0xE000E400);
+    #[cfg(not(armv6m))]
+    assert_eq!(address(&nvic.stir), 0xE000EF00);
 }
 
 #[test]