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adamgreig
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Merge #160
160: Update for 2018 edition r=korken89 a=adamgreig Co-authored-by: Adam Greig <[email protected]>
2 parents 6a21391 + 9987c6f commit 1aa7d5d

17 files changed

+62
-76
lines changed

‎CHANGELOG.md

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@@ -302,10 +302,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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#![feature(used)]
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#![no_std]
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305-
extern crate cortex_m;
306-
extern crate cortex_m_rt;
307-
extern crate stm32f30x;
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309305
use core::cell::RefCell;
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311307
use cortex_m::ctxt::Local;

‎Cargo.toml

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@@ -12,6 +12,7 @@ name = "cortex-m"
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readme = "README.md"
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repository = "https://github.com/japaric/cortex-m"
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version = "0.6.0"
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edition = "2018"
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links = "cortex-m" # prevent multiple versions of this crate to be linked together
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[dependencies]

‎src/interrupt.rs

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@@ -61,7 +61,7 @@ pub fn free<F, R>(f: F) -> R
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where
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F: FnOnce(&CriticalSection) -> R,
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{
64-
let primask = ::register::primask::read();
64+
let primask = crate::register::primask::read();
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// disable interrupts
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disable();

‎src/itm.rs

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@@ -6,7 +6,7 @@ use core::{fmt, mem, ptr, slice};
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use aligned::{Aligned, A4};
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9-
use peripheral::itm::Stim;
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use crate::peripheral::itm::Stim;
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// NOTE assumes that `bytes` is 32-bit aligned
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unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {

‎src/lib.rs

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@@ -47,4 +47,4 @@ pub mod itm;
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pub mod peripheral;
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pub mod register;
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50-
pub use peripheral::Peripherals;
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pub use crate::peripheral::Peripherals;

‎src/macros.rs

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@@ -33,8 +33,7 @@ macro_rules! iprintln {
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/// # Example
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///
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/// ``` no_run
36-
/// #[macro_use(singleton)]
37-
/// extern crate cortex_m;
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/// use cortex_m::singleton;
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///
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/// fn main() {
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/// // OK if `main` is executed only once
@@ -77,8 +76,7 @@ macro_rules! singleton {
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}
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/// ``` compile_fail
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/// #[macro_use(singleton)]
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/// extern crate cortex_m;
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/// use cortex_m::singleton;
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///
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/// fn main() {}
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///
@@ -92,8 +90,7 @@ const CFAIL: () = ();
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/// ```
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/// #![deny(unsafe_code)]
95-
/// #[macro_use(singleton)]
96-
/// extern crate cortex_m;
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/// use cortex_m::singleton;
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///
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/// fn main() {}
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///

‎src/peripheral/cbp.rs

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@@ -4,7 +4,7 @@
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use volatile_register::WO;
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7-
use peripheral::CBP;
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use crate::peripheral::CBP;
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/// Register block
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#[repr(C)]

‎src/peripheral/cpuid.rs

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@@ -5,7 +5,7 @@ use volatile_register::RO;
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use volatile_register::RW;
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#[cfg(not(armv6m))]
8-
use peripheral::CPUID;
8+
use crate::peripheral::CPUID;
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/// Register block
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#[repr(C)]
@@ -104,7 +104,7 @@ impl CPUID {
104104
const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS;
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106106
self.select_cache(level, ind);
107-
::asm::dsb();
107+
crate::asm::dsb();
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let ccsidr = self.ccsidr.read();
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(
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(1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16,

‎src/peripheral/dcb.rs

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@@ -3,7 +3,7 @@
33
use volatile_register::{RW, WO};
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55
use core::ptr;
6-
use peripheral::DCB;
6+
use crate::peripheral::DCB;
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88
const DCB_DEMCR_TRCENA: u32 = 1 << 24;
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‎src/peripheral/dwt.rs

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@@ -4,7 +4,7 @@
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use volatile_register::WO;
55
use volatile_register::{RO, RW};
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7-
use peripheral::DWT;
7+
use crate::peripheral::DWT;
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/// Register block
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#[repr(C)]

‎src/peripheral/mod.rs

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@@ -8,8 +8,6 @@
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//! the [`Peripherals::take`](struct.Peripherals.html#method.take) method.
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//!
1010
//! ``` no_run
11-
//! extern crate cortex_m;
12-
//!
1311
//! use cortex_m::peripheral::Peripherals;
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//!
1513
//! fn main() {
@@ -22,8 +20,6 @@
2220
//! `Option`. Subsequent calls to the method will result in a `None` value being returned.
2321
//!
2422
//! ``` no_run
25-
//! extern crate cortex_m;
26-
//!
2723
//! use cortex_m::peripheral::Peripherals;
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//!
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//! fn main() {
@@ -36,8 +32,6 @@
3632
//! [`DWT::get_cycle_count`](struct.DWT.html#method.get_cycle_count) method.
3733
//!
3834
//! ``` no_run
39-
//! extern crate cortex_m;
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//!
4135
//! use cortex_m::peripheral::{DWT, Peripherals};
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//!
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//! fn main() {
@@ -56,8 +50,6 @@
5650
//! safe higher level abstractions.
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//!
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//! ``` no_run
59-
//! extern crate cortex_m;
60-
//!
6153
//! use cortex_m::peripheral::{DWT, Peripherals};
6254
//!
6355
//! fn main() {
@@ -81,7 +73,7 @@
8173
use core::marker::PhantomData;
8274
use core::ops;
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84-
use interrupt;
76+
use crate::interrupt;
8577

8678
#[cfg(not(armv6m))]
8779
pub mod cbp;

‎src/peripheral/nvic.rs

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@@ -4,8 +4,8 @@ use volatile_register::RW;
44
#[cfg(not(armv6m))]
55
use volatile_register::{RO, WO};
66

7-
use interrupt::Nr;
8-
use peripheral::NVIC;
7+
use crate::interrupt::Nr;
8+
use crate::peripheral::NVIC;
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1010
/// Register block
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#[repr(C)]

‎src/peripheral/scb.rs

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@@ -321,8 +321,8 @@ impl SCB {
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// Enable I-Cache
322322
unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
323323

324-
::asm::dsb();
325-
::asm::isb();
324+
crate::asm::dsb();
325+
crate::asm::isb();
326326
}
327327

328328
/// Disables I-Cache if currently enabled
@@ -342,15 +342,15 @@ impl SCB {
342342
// Invalidate I-Cache
343343
cbp.iciallu();
344344

345-
::asm::dsb();
346-
::asm::isb();
345+
crate::asm::dsb();
346+
crate::asm::isb();
347347
}
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349349
/// Returns whether the I-Cache is currently enabled
350350
#[inline]
351351
pub fn icache_enabled() -> bool {
352-
::asm::dsb();
353-
::asm::isb();
352+
crate::asm::dsb();
353+
crate::asm::isb();
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355355
// NOTE(unsafe) atomic read with no side effects
356356
unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_IC_MASK == SCB_CCR_IC_MASK }
@@ -365,8 +365,8 @@ impl SCB {
365365
// Invalidate I-Cache
366366
cbp.iciallu();
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368-
::asm::dsb();
369-
::asm::isb();
368+
crate::asm::dsb();
369+
crate::asm::isb();
370370
}
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372372
/// Enables D-cache if currently disabled
@@ -383,8 +383,8 @@ impl SCB {
383383
// Now turn on the DCache
384384
unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
385385

386-
::asm::dsb();
387-
::asm::isb();
386+
crate::asm::dsb();
387+
crate::asm::isb();
388388
}
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390390
/// Disables D-cache if currently enabled
@@ -405,8 +405,8 @@ impl SCB {
405405
/// Returns whether the D-Cache is currently enabled
406406
#[inline]
407407
pub fn dcache_enabled() -> bool {
408-
::asm::dsb();
409-
::asm::isb();
408+
crate::asm::dsb();
409+
crate::asm::isb();
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411411
// NOTE(unsafe) atomic read with no side effects
412412
unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_DC_MASK == SCB_CCR_DC_MASK }
@@ -432,8 +432,8 @@ impl SCB {
432432
}
433433
}
434434

435-
::asm::dsb();
436-
::asm::isb();
435+
crate::asm::dsb();
436+
crate::asm::isb();
437437
}
438438

439439
/// Cleans D-cache
@@ -451,8 +451,8 @@ impl SCB {
451451
}
452452
}
453453

454-
::asm::dsb();
455-
::asm::isb();
454+
crate::asm::dsb();
455+
crate::asm::isb();
456456
}
457457

458458
/// Cleans and invalidates D-cache
@@ -470,8 +470,8 @@ impl SCB {
470470
}
471471
}
472472

473-
::asm::dsb();
474-
::asm::isb();
473+
crate::asm::dsb();
474+
crate::asm::isb();
475475
}
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477477
/// Invalidates D-cache by address
@@ -491,7 +491,7 @@ impl SCB {
491491
// NOTE(unsafe) All CBP registers are write-only and stateless
492492
let mut cbp = unsafe { CBP::new() };
493493

494-
::asm::dsb();
494+
crate::asm::dsb();
495495

496496
// Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
497497
const LINESIZE: usize = 32;
@@ -504,8 +504,8 @@ impl SCB {
504504
addr += LINESIZE;
505505
}
506506

507-
::asm::dsb();
508-
::asm::isb();
507+
crate::asm::dsb();
508+
crate::asm::isb();
509509
}
510510

511511
/// Cleans D-cache by address
@@ -525,7 +525,7 @@ impl SCB {
525525
// NOTE(unsafe) All CBP registers are write-only and stateless
526526
let mut cbp = unsafe { CBP::new() };
527527

528-
::asm::dsb();
528+
crate::asm::dsb();
529529

530530
// Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
531531
const LINESIZE: usize = 32;
@@ -538,8 +538,8 @@ impl SCB {
538538
addr += LINESIZE;
539539
}
540540

541-
::asm::dsb();
542-
::asm::isb();
541+
crate::asm::dsb();
542+
crate::asm::isb();
543543
}
544544

545545
/// Cleans and invalidates D-cache by address
@@ -560,7 +560,7 @@ impl SCB {
560560
// NOTE(unsafe) All CBP registers are write-only and stateless
561561
let mut cbp = unsafe { CBP::new() };
562562

563-
::asm::dsb();
563+
crate::asm::dsb();
564564

565565
// Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
566566
const LINESIZE: usize = 32;
@@ -573,8 +573,8 @@ impl SCB {
573573
addr += LINESIZE;
574574
}
575575

576-
::asm::dsb();
577-
::asm::isb();
576+
crate::asm::dsb();
577+
crate::asm::isb();
578578
}
579579
}
580580

@@ -622,7 +622,7 @@ impl SCB {
622622
/// Initiate a system reset request to reset the MCU
623623
#[deprecated(since = "0.6.1", note = "Use `SCB::sys_reset`")]
624624
pub fn system_reset(&mut self) -> ! {
625-
::asm::dsb();
625+
crate::asm::dsb();
626626
unsafe {
627627
self.aircr.modify(
628628
|r| {
@@ -632,16 +632,16 @@ impl SCB {
632632
}, // set the bit
633633
)
634634
};
635-
::asm::dsb();
635+
crate::asm::dsb();
636636
loop {
637637
// wait for the reset
638-
::asm::nop(); // avoid rust-lang/rust#28728
638+
crate::asm::nop(); // avoid rust-lang/rust#28728
639639
}
640640
}
641641

642642
/// Initiate a system reset request to reset the MCU
643643
pub fn sys_reset() -> ! {
644-
::asm::dsb();
644+
crate::asm::dsb();
645645
unsafe {
646646
(*Self::ptr()).aircr.modify(
647647
|r| {
@@ -651,10 +651,10 @@ impl SCB {
651651
}, // set the bit
652652
)
653653
};
654-
::asm::dsb();
654+
crate::asm::dsb();
655655
loop {
656656
// wait for the reset
657-
::asm::nop(); // avoid rust-lang/rust#28728
657+
crate::asm::nop(); // avoid rust-lang/rust#28728
658658
}
659659
}
660660
}

‎src/peripheral/syst.rs

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@@ -2,7 +2,7 @@
22
33
use volatile_register::{RO, RW};
44

5-
use peripheral::SYST;
5+
use crate::peripheral::SYST;
66

77
/// Register block
88
#[repr(C)]

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