Skip to content

Commit 3607c6c

Browse files
bors[bot]m-ou-se
bors[bot]
and
m-ou-se
authored
Merge #171
171: Add `#[inline]` to lots of trivial functions. r=korken89 a=m-ou-se Now the only public non-inline functions left are: - `write_all` - `write_aligned` - All (derived) `Debug` implementations (Checked using Clippy's [`missing_inline_in_public_items`][1] lint.) [1]: https://rust-lang.github.io/rust-clippy/master/#missing_inline_in_public_items Co-authored-by: Mara Bos <[email protected]>
2 parents 0e06c94 + 90c4717 commit 3607c6c

File tree

13 files changed

+103
-0
lines changed

13 files changed

+103
-0
lines changed

‎src/interrupt.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ pub unsafe fn enable() {
5757
/// Execute closure `f` in an interrupt-free context.
5858
///
5959
/// This as also known as a "critical section".
60+
#[inline]
6061
pub fn free<F, R>(f: F) -> R
6162
where
6263
F: FnOnce(&CriticalSection) -> R,

‎src/itm.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {
2121
struct Port<'p>(&'p mut Stim);
2222

2323
impl<'p> fmt::Write for Port<'p> {
24+
#[inline]
2425
fn write_str(&mut self, s: &str) -> fmt::Result {
2526
write_all(self.0, s.as_bytes());
2627
Ok(())
@@ -126,13 +127,15 @@ pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) {
126127
}
127128

128129
/// Writes `fmt::Arguments` to the ITM `port`
130+
#[inline]
129131
pub fn write_fmt(port: &mut Stim, args: fmt::Arguments) {
130132
use core::fmt::Write;
131133

132134
Port(port).write_fmt(args).ok();
133135
}
134136

135137
/// Writes a string to the ITM `port`
138+
#[inline]
136139
pub fn write_str(port: &mut Stim, string: &str) {
137140
write_all(port, string.as_bytes())
138141
}

‎src/peripheral/cpuid.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,7 @@ impl CPUID {
8282
/// * `ind`: select instruction cache or data/unified cache
8383
///
8484
/// `level` is masked to be between 0 and 7.
85+
#[inline]
8586
pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType) {
8687
const CSSELR_IND_POS: u32 = 0;
8788
const CSSELR_IND_MASK: u32 = 1 << CSSELR_IND_POS;
@@ -97,6 +98,7 @@ impl CPUID {
9798
}
9899

99100
/// Returns the number of sets and ways in the selected cache
101+
#[inline]
100102
pub fn cache_num_sets_ways(&mut self, level: u8, ind: CsselrCacheType) -> (u16, u16) {
101103
const CCSIDR_NUMSETS_POS: u32 = 13;
102104
const CCSIDR_NUMSETS_MASK: u32 = 0x7FFF << CCSIDR_NUMSETS_POS;

‎src/peripheral/dcb.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ impl DCB {
2525
/// `peripheral::DWT` cycle counter to work properly.
2626
/// As by STM documentation, this flag is not reset on
2727
/// soft-reset, only on power reset.
28+
#[inline]
2829
pub fn enable_trace(&mut self) {
2930
// set bit 24 / TRCENA
3031
unsafe {
@@ -33,6 +34,7 @@ impl DCB {
3334
}
3435

3536
/// Disables TRACE. See `DCB::enable_trace()` for more details
37+
#[inline]
3638
pub fn disable_trace(&mut self) {
3739
// unset bit 24 / TRCENA
3840
unsafe {
@@ -47,6 +49,7 @@ impl DCB {
4749
/// on Cortex-M0 devices. Per the ARM v6-M Architecture Reference Manual, "Access to the DHCSR
4850
/// from software running on the processor is IMPLEMENTATION DEFINED". Indeed, from the
4951
/// [Cortex-M0+ r0p1 Technical Reference Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0484c/BABJHEIG.html), "Note Software cannot access the debug registers."
52+
#[inline]
5053
pub fn is_debugger_attached() -> bool {
5154
unsafe {
5255
// do an 8-bit read of the 32-bit DHCSR register, and get the LSB

‎src/peripheral/dwt.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,12 +65,14 @@ pub struct Comparator {
6565
impl DWT {
6666
/// Enables the cycle counter
6767
#[cfg(not(armv6m))]
68+
#[inline]
6869
pub fn enable_cycle_counter(&mut self) {
6970
unsafe { self.ctrl.modify(|r| r | 1) }
7071
}
7172

7273
/// Returns the current clock cycle count
7374
#[cfg(not(armv6m))]
75+
#[inline]
7476
pub fn get_cycle_count() -> u32 {
7577
// NOTE(unsafe) atomic read with no side effects
7678
unsafe { (*Self::ptr()).cyccnt.read() }
@@ -80,6 +82,7 @@ impl DWT {
8082
///
8183
/// Some devices, like the STM32F7, software lock the DWT after a power cycle.
8284
#[cfg(not(armv6m))]
85+
#[inline]
8386
pub fn unlock() {
8487
// NOTE(unsafe) atomic write to a stateless, write-only register
8588
unsafe { (*Self::ptr()).lar.write(0xC5AC_CE55) }

‎src/peripheral/itm.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,21 +35,25 @@ pub struct Stim {
3535

3636
impl Stim {
3737
/// Writes an `u8` payload into the stimulus port
38+
#[inline]
3839
pub fn write_u8(&mut self, value: u8) {
3940
unsafe { ptr::write_volatile(self.register.get() as *mut u8, value) }
4041
}
4142

4243
/// Writes an `u16` payload into the stimulus port
44+
#[inline]
4345
pub fn write_u16(&mut self, value: u16) {
4446
unsafe { ptr::write_volatile(self.register.get() as *mut u16, value) }
4547
}
4648

4749
/// Writes an `u32` payload into the stimulus port
50+
#[inline]
4851
pub fn write_u32(&mut self, value: u32) {
4952
unsafe { ptr::write_volatile(self.register.get(), value) }
5053
}
5154

5255
/// Returns `true` if the stimulus port is ready to accept more data
56+
#[inline]
5357
pub fn is_fifo_ready(&self) -> bool {
5458
unsafe { ptr::read_volatile(self.register.get()) == 1 }
5559
}

‎src/peripheral/mod.rs

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,7 @@ impl Peripherals {
159159
}
160160

161161
/// Unchecked version of `Peripherals::take`
162+
#[inline]
162163
pub unsafe fn steal() -> Self {
163164
CORE_PERIPHERALS = true;
164165

@@ -212,13 +213,15 @@ unsafe impl Send for CBP {}
212213

213214
#[cfg(not(armv6m))]
214215
impl CBP {
216+
#[inline(always)]
215217
pub(crate) unsafe fn new() -> Self {
216218
CBP {
217219
_marker: PhantomData,
218220
}
219221
}
220222

221223
/// Returns a pointer to the register block
224+
#[inline(always)]
222225
pub fn ptr() -> *const self::cbp::RegisterBlock {
223226
0xE000_EF50 as *const _
224227
}
@@ -228,6 +231,7 @@ impl CBP {
228231
impl ops::Deref for CBP {
229232
type Target = self::cbp::RegisterBlock;
230233

234+
#[inline(always)]
231235
fn deref(&self) -> &Self::Target {
232236
unsafe { &*Self::ptr() }
233237
}
@@ -242,6 +246,7 @@ unsafe impl Send for CPUID {}
242246

243247
impl CPUID {
244248
/// Returns a pointer to the register block
249+
#[inline(always)]
245250
pub fn ptr() -> *const self::cpuid::RegisterBlock {
246251
0xE000_ED00 as *const _
247252
}
@@ -250,6 +255,7 @@ impl CPUID {
250255
impl ops::Deref for CPUID {
251256
type Target = self::cpuid::RegisterBlock;
252257

258+
#[inline(always)]
253259
fn deref(&self) -> &Self::Target {
254260
unsafe { &*Self::ptr() }
255261
}
@@ -264,6 +270,7 @@ unsafe impl Send for DCB {}
264270

265271
impl DCB {
266272
/// Returns a pointer to the register block
273+
#[inline(always)]
267274
pub fn ptr() -> *const dcb::RegisterBlock {
268275
0xE000_EDF0 as *const _
269276
}
@@ -272,6 +279,7 @@ impl DCB {
272279
impl ops::Deref for DCB {
273280
type Target = self::dcb::RegisterBlock;
274281

282+
#[inline(always)]
275283
fn deref(&self) -> &Self::Target {
276284
unsafe { &*DCB::ptr() }
277285
}
@@ -286,6 +294,7 @@ unsafe impl Send for DWT {}
286294

287295
impl DWT {
288296
/// Returns a pointer to the register block
297+
#[inline(always)]
289298
pub fn ptr() -> *const dwt::RegisterBlock {
290299
0xE000_1000 as *const _
291300
}
@@ -294,6 +303,7 @@ impl DWT {
294303
impl ops::Deref for DWT {
295304
type Target = self::dwt::RegisterBlock;
296305

306+
#[inline(always)]
297307
fn deref(&self) -> &Self::Target {
298308
unsafe { &*Self::ptr() }
299309
}
@@ -309,6 +319,7 @@ unsafe impl Send for FPB {}
309319
#[cfg(not(armv6m))]
310320
impl FPB {
311321
/// Returns a pointer to the register block
322+
#[inline(always)]
312323
pub fn ptr() -> *const fpb::RegisterBlock {
313324
0xE000_2000 as *const _
314325
}
@@ -318,6 +329,7 @@ impl FPB {
318329
impl ops::Deref for FPB {
319330
type Target = self::fpb::RegisterBlock;
320331

332+
#[inline(always)]
321333
fn deref(&self) -> &Self::Target {
322334
unsafe { &*Self::ptr() }
323335
}
@@ -333,6 +345,7 @@ unsafe impl Send for FPU {}
333345
#[cfg(any(has_fpu, target_arch = "x86_64"))]
334346
impl FPU {
335347
/// Returns a pointer to the register block
348+
#[inline(always)]
336349
pub fn ptr() -> *const fpu::RegisterBlock {
337350
0xE000_EF30 as *const _
338351
}
@@ -342,6 +355,7 @@ impl FPU {
342355
impl ops::Deref for FPU {
343356
type Target = self::fpu::RegisterBlock;
344357

358+
#[inline(always)]
345359
fn deref(&self) -> &Self::Target {
346360
unsafe { &*Self::ptr() }
347361
}
@@ -357,6 +371,7 @@ unsafe impl Send for ITM {}
357371
#[cfg(not(armv6m))]
358372
impl ITM {
359373
/// Returns a pointer to the register block
374+
#[inline(always)]
360375
pub fn ptr() -> *mut itm::RegisterBlock {
361376
0xE000_0000 as *mut _
362377
}
@@ -366,13 +381,15 @@ impl ITM {
366381
impl ops::Deref for ITM {
367382
type Target = self::itm::RegisterBlock;
368383

384+
#[inline(always)]
369385
fn deref(&self) -> &Self::Target {
370386
unsafe { &*Self::ptr() }
371387
}
372388
}
373389

374390
#[cfg(not(armv6m))]
375391
impl ops::DerefMut for ITM {
392+
#[inline(always)]
376393
fn deref_mut(&mut self) -> &mut Self::Target {
377394
unsafe { &mut *Self::ptr() }
378395
}
@@ -387,6 +404,7 @@ unsafe impl Send for MPU {}
387404

388405
impl MPU {
389406
/// Returns a pointer to the register block
407+
#[inline(always)]
390408
pub fn ptr() -> *const mpu::RegisterBlock {
391409
0xE000_ED90 as *const _
392410
}
@@ -395,6 +413,7 @@ impl MPU {
395413
impl ops::Deref for MPU {
396414
type Target = self::mpu::RegisterBlock;
397415

416+
#[inline(always)]
398417
fn deref(&self) -> &Self::Target {
399418
unsafe { &*Self::ptr() }
400419
}
@@ -409,6 +428,7 @@ unsafe impl Send for NVIC {}
409428

410429
impl NVIC {
411430
/// Returns a pointer to the register block
431+
#[inline(always)]
412432
pub fn ptr() -> *const nvic::RegisterBlock {
413433
0xE000_E100 as *const _
414434
}
@@ -417,6 +437,7 @@ impl NVIC {
417437
impl ops::Deref for NVIC {
418438
type Target = self::nvic::RegisterBlock;
419439

440+
#[inline(always)]
420441
fn deref(&self) -> &Self::Target {
421442
unsafe { &*Self::ptr() }
422443
}
@@ -431,6 +452,7 @@ unsafe impl Send for SCB {}
431452

432453
impl SCB {
433454
/// Returns a pointer to the register block
455+
#[inline(always)]
434456
pub fn ptr() -> *const scb::RegisterBlock {
435457
0xE000_ED04 as *const _
436458
}
@@ -439,6 +461,7 @@ impl SCB {
439461
impl ops::Deref for SCB {
440462
type Target = self::scb::RegisterBlock;
441463

464+
#[inline(always)]
442465
fn deref(&self) -> &Self::Target {
443466
unsafe { &*Self::ptr() }
444467
}
@@ -453,6 +476,7 @@ unsafe impl Send for SYST {}
453476

454477
impl SYST {
455478
/// Returns a pointer to the register block
479+
#[inline(always)]
456480
pub fn ptr() -> *const syst::RegisterBlock {
457481
0xE000_E010 as *const _
458482
}
@@ -461,6 +485,7 @@ impl SYST {
461485
impl ops::Deref for SYST {
462486
type Target = self::syst::RegisterBlock;
463487

488+
#[inline(always)]
464489
fn deref(&self) -> &Self::Target {
465490
unsafe { &*Self::ptr() }
466491
}
@@ -476,6 +501,7 @@ unsafe impl Send for TPIU {}
476501
#[cfg(not(armv6m))]
477502
impl TPIU {
478503
/// Returns a pointer to the register block
504+
#[inline(always)]
479505
pub fn ptr() -> *const tpiu::RegisterBlock {
480506
0xE004_0000 as *const _
481507
}
@@ -485,6 +511,7 @@ impl TPIU {
485511
impl ops::Deref for TPIU {
486512
type Target = self::tpiu::RegisterBlock;
487513

514+
#[inline(always)]
488515
fn deref(&self) -> &Self::Target {
489516
unsafe { &*Self::ptr() }
490517
}

0 commit comments

Comments
 (0)