Skip to content

Commit a7b9cb9

Browse files
bors[bot]bytex64
andcommitted
Merge #168
168: On HardFault entry use MSP/PSP depending on stack mode r=thejpster a=bytex64 Noticed this when making my own hardfault handler - none of the registers were correct. The `&ExceptionFrame` argument was wrong because I was using the PSP in Thread mode, but the handler only loads MSP. This PR inspects the EXC_RETURN value in LR and loads either MSP or PSP depending on the stack used (see section B1.5.8 in the ARMv7-M architecture manual for details on the format of EXC_RETURN). I haven't tested this on armv6m or armv8m, but I believe it works the same across the board. Also didn't update the libraries in `bin/` since I wasn't sure if that was expected or not. Co-authored-by: Chip <[email protected]>
2 parents 3436a11 + 99409a2 commit a7b9cb9

6 files changed

+9
-0
lines changed

cortex-m-rt/asm.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,5 +6,14 @@
66
.type HardFaultTrampoline,%function
77
.thumb_func
88
HardFaultTrampoline:
9+
# depending on the stack mode in EXC_RETURN, fetch stack pointer from
10+
# PSP or MSP
11+
mov r0, lr
12+
mov r1, #4
13+
tst r0, r1
14+
bne 0f
915
mrs r0, MSP
1016
b HardFault
17+
0:
18+
mrs r0, PSP
19+
b HardFault

cortex-m-rt/bin/thumbv6m-none-eabi.a

20 Bytes
Binary file not shown.

cortex-m-rt/bin/thumbv7em-none-eabi.a

20 Bytes
Binary file not shown.
20 Bytes
Binary file not shown.

cortex-m-rt/bin/thumbv7m-none-eabi.a

20 Bytes
Binary file not shown.
20 Bytes
Binary file not shown.

0 commit comments

Comments
 (0)