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Make clippy happy, again.
1 parent f505673 commit ab7ed07

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6 files changed

+7
-9
lines changed

6 files changed

+7
-9
lines changed

src/lib.rs

+1
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333
#![deny(missing_docs)]
3434
#![no_std]
3535
#![allow(clippy::identity_op)]
36+
#![allow(clippy::missing_safety_doc)]
3637

3738
extern crate aligned;
3839
extern crate bare_metal;

src/macros.rs

-4
Original file line numberDiff line numberDiff line change
@@ -78,8 +78,6 @@ macro_rules! singleton {
7878
/// ``` compile_fail
7979
/// use cortex_m::singleton;
8080
///
81-
/// fn main() {}
82-
///
8381
/// fn foo() {
8482
/// // check that the call to `uninitialized` requires unsafe
8583
/// singleton!(: u8 = std::mem::uninitialized());
@@ -92,8 +90,6 @@ const CFAIL: () = ();
9290
/// #![deny(unsafe_code)]
9391
/// use cortex_m::singleton;
9492
///
95-
/// fn main() {}
96-
///
9793
/// fn foo() {
9894
/// // check that calls to `singleton!` don't trip the `unsafe_code` lint
9995
/// singleton!(: u8 = 0);

src/peripheral/dwt.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,6 @@ impl DWT {
8282
#[cfg(not(armv6m))]
8383
pub fn unlock() {
8484
// NOTE(unsafe) atomic write to a stateless, write-only register
85-
unsafe { (*Self::ptr()).lar.write(0xC5ACCE55) }
85+
unsafe { (*Self::ptr()).lar.write(0xC5AC_CE55) }
8686
}
8787
}

src/peripheral/mod.rs

+1
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
#![allow(clippy::needless_doctest_main)]
12
//! Core peripherals
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//!
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//! # API

src/peripheral/nvic.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ impl NVIC {
164164
{
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// NOTE(unsafe) atomic read with no side effects
166166
let ipr_n = unsafe { (*Self::ptr()).ipr[Self::ipr_index(&interrupt)].read() };
167-
let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x000000ff;
167+
let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x0000_00ff;
168168
prio as u8
169169
}
170170
}
@@ -251,7 +251,7 @@ impl NVIC {
251251
#[cfg(armv6m)]
252252
{
253253
self.ipr[Self::ipr_index(&interrupt)].modify(|value| {
254-
let mask = 0x000000ff << Self::ipr_shift(&interrupt);
254+
let mask = 0x0000_00ff << Self::ipr_shift(&interrupt);
255255
let prio = u32::from(prio) << Self::ipr_shift(&interrupt);
256256

257257
(value & !mask) | prio

src/peripheral/scb.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,7 @@ impl SCB {
781781
{
782782
// NOTE(unsafe) atomic read with no side effects
783783
let shpr = unsafe { (*Self::ptr()).shpr[usize::from((index - 8) / 4)].read() };
784-
let prio = (shpr >> (8 * (index % 4))) & 0x000000ff;
784+
let prio = (shpr >> (8 * (index % 4))) & 0x0000_00ff;
785785
prio as u8
786786
}
787787
}
@@ -810,7 +810,7 @@ impl SCB {
810810
{
811811
self.shpr[usize::from((index - 8) / 4)].modify(|value| {
812812
let shift = 8 * (index % 4);
813-
let mask = 0x000000ff << shift;
813+
let mask = 0x0000_00ff << shift;
814814
let prio = u32::from(prio) << shift;
815815

816816
(value & !mask) | prio

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