Add new InterruptNumber trait

Author: adamgreig

src/interrupt.rs

@@ -1,8 +1,22 @@
 //! Interrupts
 
-// use core::sync::atomic::{self, Ordering};
+pub use bare_metal::{CriticalSection, Mutex};
 
-pub use bare_metal::{CriticalSection, Mutex, Nr};
+/// Trait for enums of external interrupt numbers.
+///
+/// This trait should be implemented by a peripheral access crate (PAC)
+/// on its enum of available external interrupts for a specific device.
+/// Each variant must convert to a u16 of its interrupt number,
+/// which is its exception number - 16.
+///
+/// # Safety
+///
+/// This trait must only be implemented on enums of device interrupts. Each
+/// enum variant must represent a distinct value (no duplicates are permitted),
+/// and must always return the same value (do not change at runtime).
+///
+/// These requirements ensure safe nesting of critical sections.
+pub unsafe trait InterruptNumber: Into<u16> {}
 
 /// Disables all interrupts
 #[inline]

src/peripheral/nvic.rs

@@ -4,7 +4,7 @@ use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};
 
-use crate::interrupt::Nr;
+use crate::interrupt::InterruptNumber;
 use crate::peripheral::NVIC;
 
 /// Register block
@@ -86,9 +86,9 @@ impl NVIC {
     #[inline]
     pub fn request<I>(&mut self, interrupt: I)
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
 
         unsafe {
             self.stir.write(u32::from(nr));
@@ -99,9 +99,9 @@ impl NVIC {
     #[inline]
     pub fn mask<I>(interrupt: I)
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
         // NOTE(unsafe) this is a write to a stateless register
         unsafe { (*Self::ptr()).icer[usize::from(nr / 32)].write(1 << (nr % 32)) }
     }
@@ -112,9 +112,9 @@ impl NVIC {
     #[inline]
     pub unsafe fn unmask<I>(interrupt: I)
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
         // NOTE(ptr) this is a write to a stateless register
         (*Self::ptr()).iser[usize::from(nr / 32)].write(1 << (nr % 32))
     }
@@ -127,11 +127,11 @@ impl NVIC {
     #[inline]
     pub fn get_priority<I>(interrupt: I) -> u8
     where
-        I: Nr,
+        I: InterruptNumber,
     {
         #[cfg(not(armv6m))]
         {
-            let nr = interrupt.nr();
+            let nr = interrupt.into();
             // NOTE(unsafe) atomic read with no side effects
             unsafe { (*Self::ptr()).ipr[usize::from(nr)].read() }
         }
@@ -150,9 +150,9 @@ impl NVIC {
     #[inline]
     pub fn is_active<I>(interrupt: I) -> bool
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
         let mask = 1 << (nr % 32);
 
         // NOTE(unsafe) atomic read with no side effects
@@ -163,9 +163,9 @@ impl NVIC {
     #[inline]
     pub fn is_enabled<I>(interrupt: I) -> bool
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
         let mask = 1 << (nr % 32);
 
         // NOTE(unsafe) atomic read with no side effects
@@ -176,9 +176,9 @@ impl NVIC {
     #[inline]
     pub fn is_pending<I>(interrupt: I) -> bool
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
         let mask = 1 << (nr % 32);
 
         // NOTE(unsafe) atomic read with no side effects
@@ -189,9 +189,9 @@ impl NVIC {
     #[inline]
     pub fn pend<I>(interrupt: I)
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
 
         // NOTE(unsafe) atomic stateless write; ICPR doesn't store any state
         unsafe { (*Self::ptr()).ispr[usize::from(nr / 32)].write(1 << (nr % 32)) }
@@ -212,11 +212,11 @@ impl NVIC {
     #[inline]
     pub unsafe fn set_priority<I>(&mut self, interrupt: I, prio: u8)
     where
-        I: Nr,
+        I: InterruptNumber,
     {
         #[cfg(not(armv6m))]
         {
-            let nr = interrupt.nr();
+            let nr = interrupt.into();
             self.ipr[usize::from(nr)].write(prio)
         }
 
@@ -235,9 +235,9 @@ impl NVIC {
     #[inline]
     pub fn unpend<I>(interrupt: I)
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        let nr = interrupt.nr();
+        let nr = interrupt.into();
 
         // NOTE(unsafe) atomic stateless write; ICPR doesn't store any state
         unsafe { (*Self::ptr()).icpr[usize::from(nr / 32)].write(1 << (nr % 32)) }
@@ -247,17 +247,17 @@ impl NVIC {
     #[inline]
     fn ipr_index<I>(interrupt: &I) -> usize
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        usize::from(interrupt.nr()) / 4
+        usize::from(interrupt.into()) / 4
     }
 
     #[cfg(armv6m)]
     #[inline]
     fn ipr_shift<I>(interrupt: &I) -> usize
     where
-        I: Nr,
+        I: InterruptNumber,
     {
-        (usize::from(interrupt.nr()) % 4) * 8
+        (usize::from(interrupt.into()) % 4) * 8
     }
 }