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[WebAssembly] Codegen for pmin and pmax
Replace the clang builtins and LLVM intrinsics for {f32x4,f64x2}.{pmin,pmax} with standard codegen patterns. Since wasm_simd128.h uses an integer vector as the standard single vector type, the IR for the pmin and pmax intrinsic functions contains bitcasts that would not be there otherwise. Add extra codegen patterns that can still select the pmin and pmax instructions in the presence of these bitcasts. Differential Revision: https://reviews.llvm.org/D106612
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+142
-116
lines changed

9 files changed

+142
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‎clang/include/clang/Basic/BuiltinsWebAssembly.def

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -144,12 +144,8 @@ TARGET_BUILTIN(__builtin_wasm_abs_f64x2, "V2dV2d", "nc", "simd128")
144144

145145
TARGET_BUILTIN(__builtin_wasm_min_f32x4, "V4fV4fV4f", "nc", "simd128")
146146
TARGET_BUILTIN(__builtin_wasm_max_f32x4, "V4fV4fV4f", "nc", "simd128")
147-
TARGET_BUILTIN(__builtin_wasm_pmin_f32x4, "V4fV4fV4f", "nc", "simd128")
148-
TARGET_BUILTIN(__builtin_wasm_pmax_f32x4, "V4fV4fV4f", "nc", "simd128")
149147
TARGET_BUILTIN(__builtin_wasm_min_f64x2, "V2dV2dV2d", "nc", "simd128")
150148
TARGET_BUILTIN(__builtin_wasm_max_f64x2, "V2dV2dV2d", "nc", "simd128")
151-
TARGET_BUILTIN(__builtin_wasm_pmin_f64x2, "V2dV2dV2d", "nc", "simd128")
152-
TARGET_BUILTIN(__builtin_wasm_pmax_f64x2, "V2dV2dV2d", "nc", "simd128")
153149

154150
TARGET_BUILTIN(__builtin_wasm_ceil_f32x4, "V4fV4f", "nc", "simd128")
155151
TARGET_BUILTIN(__builtin_wasm_floor_f32x4, "V4fV4f", "nc", "simd128")

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -17589,22 +17589,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1758917589
CGM.getIntrinsic(Intrinsic::maximum, ConvertType(E->getType()));
1759017590
return Builder.CreateCall(Callee, {LHS, RHS});
1759117591
}
17592-
case WebAssembly::BI__builtin_wasm_pmin_f32x4:
17593-
case WebAssembly::BI__builtin_wasm_pmin_f64x2: {
17594-
Value *LHS = EmitScalarExpr(E->getArg(0));
17595-
Value *RHS = EmitScalarExpr(E->getArg(1));
17596-
Function *Callee =
17597-
CGM.getIntrinsic(Intrinsic::wasm_pmin, ConvertType(E->getType()));
17598-
return Builder.CreateCall(Callee, {LHS, RHS});
17599-
}
17600-
case WebAssembly::BI__builtin_wasm_pmax_f32x4:
17601-
case WebAssembly::BI__builtin_wasm_pmax_f64x2: {
17602-
Value *LHS = EmitScalarExpr(E->getArg(0));
17603-
Value *RHS = EmitScalarExpr(E->getArg(1));
17604-
Function *Callee =
17605-
CGM.getIntrinsic(Intrinsic::wasm_pmax, ConvertType(E->getType()));
17606-
return Builder.CreateCall(Callee, {LHS, RHS});
17607-
}
1760817592
case WebAssembly::BI__builtin_wasm_ceil_f32x4:
1760917593
case WebAssembly::BI__builtin_wasm_floor_f32x4:
1761017594
case WebAssembly::BI__builtin_wasm_trunc_f32x4:

‎clang/lib/Headers/wasm_simd128.h

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1150,12 +1150,14 @@ static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f32x4_max(v128_t __a,
11501150

11511151
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f32x4_pmin(v128_t __a,
11521152
v128_t __b) {
1153-
return (v128_t)__builtin_wasm_pmin_f32x4((__f32x4)__a, (__f32x4)__b);
1153+
__i32x4 __mask = (__i32x4)((__f32x4)__b < (__f32x4)__a);
1154+
return (v128_t)((((__i32x4)__b) & __mask) | (((__i32x4)__a) & ~__mask));
11541155
}
11551156

11561157
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f32x4_pmax(v128_t __a,
11571158
v128_t __b) {
1158-
return (v128_t)__builtin_wasm_pmax_f32x4((__f32x4)__a, (__f32x4)__b);
1159+
__i32x4 __mask = (__i32x4)((__f32x4)__a < (__f32x4)__b);
1160+
return (v128_t)((((__i32x4)__b) & __mask) | (((__i32x4)__a) & ~__mask));
11591161
}
11601162

11611163
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f64x2_abs(v128_t __a) {
@@ -1218,12 +1220,14 @@ static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f64x2_max(v128_t __a,
12181220

12191221
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f64x2_pmin(v128_t __a,
12201222
v128_t __b) {
1221-
return (v128_t)__builtin_wasm_pmin_f64x2((__f64x2)__a, (__f64x2)__b);
1223+
__i64x2 __mask = (__i64x2)((__f64x2)__b < (__f64x2)__a);
1224+
return (v128_t)((((__i64x2)__b) & __mask) | (((__i64x2)__a) & ~__mask));
12221225
}
12231226

12241227
static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_f64x2_pmax(v128_t __a,
12251228
v128_t __b) {
1226-
return (v128_t)__builtin_wasm_pmax_f64x2((__f64x2)__a, (__f64x2)__b);
1229+
__i64x2 __mask = (__i64x2)((__f64x2)__a < (__f64x2)__b);
1230+
return (v128_t)((((__i64x2)__b) & __mask) | (((__i64x2)__a) & ~__mask));
12271231
}
12281232

12291233
static __inline__ v128_t __DEFAULT_FN_ATTRS

‎clang/test/CodeGen/builtins-wasm.c

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -590,20 +590,6 @@ f32x4 max_f32x4(f32x4 x, f32x4 y) {
590590
// WEBASSEMBLY-NEXT: ret
591591
}
592592

593-
f32x4 pmin_f32x4(f32x4 x, f32x4 y) {
594-
return __builtin_wasm_pmin_f32x4(x, y);
595-
// WEBASSEMBLY: call <4 x float> @llvm.wasm.pmin.v4f32(
596-
// WEBASSEMBLY-SAME: <4 x float> %x, <4 x float> %y)
597-
// WEBASSEMBLY-NEXT: ret
598-
}
599-
600-
f32x4 pmax_f32x4(f32x4 x, f32x4 y) {
601-
return __builtin_wasm_pmax_f32x4(x, y);
602-
// WEBASSEMBLY: call <4 x float> @llvm.wasm.pmax.v4f32(
603-
// WEBASSEMBLY-SAME: <4 x float> %x, <4 x float> %y)
604-
// WEBASSEMBLY-NEXT: ret
605-
}
606-
607593
f64x2 min_f64x2(f64x2 x, f64x2 y) {
608594
return __builtin_wasm_min_f64x2(x, y);
609595
// WEBASSEMBLY: call <2 x double> @llvm.minimum.v2f64(
@@ -618,20 +604,6 @@ f64x2 max_f64x2(f64x2 x, f64x2 y) {
618604
// WEBASSEMBLY-NEXT: ret
619605
}
620606

621-
f64x2 pmin_f64x2(f64x2 x, f64x2 y) {
622-
return __builtin_wasm_pmin_f64x2(x, y);
623-
// WEBASSEMBLY: call <2 x double> @llvm.wasm.pmin.v2f64(
624-
// WEBASSEMBLY-SAME: <2 x double> %x, <2 x double> %y)
625-
// WEBASSEMBLY-NEXT: ret
626-
}
627-
628-
f64x2 pmax_f64x2(f64x2 x, f64x2 y) {
629-
return __builtin_wasm_pmax_f64x2(x, y);
630-
// WEBASSEMBLY: call <2 x double> @llvm.wasm.pmax.v2f64(
631-
// WEBASSEMBLY-SAME: <2 x double> %x, <2 x double> %y)
632-
// WEBASSEMBLY-NEXT: ret
633-
}
634-
635607
f32x4 ceil_f32x4(f32x4 x) {
636608
return __builtin_wasm_ceil_f32x4(x);
637609
// WEBASSEMBLY: call <4 x float> @llvm.ceil.v4f32(<4 x float> %x)

‎clang/test/Headers/wasm.c

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2191,11 +2191,11 @@ v128_t test_f32x4_max(v128_t a, v128_t b) {
21912191

21922192
// CHECK-LABEL: @test_f32x4_pmin(
21932193
// CHECK-NEXT: entry:
2194-
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <4 x float>
2195-
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <4 x float>
2196-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> [[TMP0]], <4 x float> [[TMP1]]) #[[ATTR6]]
2197-
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x float> [[TMP2]] to <4 x i32>
2198-
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
2194+
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B:%.*]] to <4 x float>
2195+
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[A:%.*]] to <4 x float>
2196+
// CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt <4 x float> [[TMP0]], [[TMP1]]
2197+
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[CMP_I]], <4 x i32> [[B]], <4 x i32> [[A]]
2198+
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
21992199
//
22002200
v128_t test_f32x4_pmin(v128_t a, v128_t b) {
22012201
return wasm_f32x4_pmin(a, b);
@@ -2205,9 +2205,9 @@ v128_t test_f32x4_pmin(v128_t a, v128_t b) {
22052205
// CHECK-NEXT: entry:
22062206
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <4 x float>
22072207
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <4 x float>
2208-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> [[TMP0]], <4 x float> [[TMP1]]) #[[ATTR6]]
2209-
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x float> [[TMP2]] to <4 x i32>
2210-
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
2208+
// CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt <4 x float> [[TMP0]], [[TMP1]]
2209+
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[CMP_I]], <4 x i32> [[B]], <4 x i32> [[A]]
2210+
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
22112211
//
22122212
v128_t test_f32x4_pmax(v128_t a, v128_t b) {
22132213
return wasm_f32x4_pmax(a, b);
@@ -2364,9 +2364,10 @@ v128_t test_f64x2_max(v128_t a, v128_t b) {
23642364

23652365
// CHECK-LABEL: @test_f64x2_pmin(
23662366
// CHECK-NEXT: entry:
2367-
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x double>
2368-
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <2 x double>
2369-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> [[TMP0]], <2 x double> [[TMP1]]) #[[ATTR6]]
2367+
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B:%.*]] to <2 x double>
2368+
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x double>
2369+
// CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt <2 x double> [[TMP0]], [[TMP1]]
2370+
// CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[CMP_I]], <2 x double> [[TMP0]], <2 x double> [[TMP1]]
23702371
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x double> [[TMP2]] to <4 x i32>
23712372
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
23722373
//
@@ -2378,7 +2379,8 @@ v128_t test_f64x2_pmin(v128_t a, v128_t b) {
23782379
// CHECK-NEXT: entry:
23792380
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x double>
23802381
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <2 x double>
2381-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> [[TMP0]], <2 x double> [[TMP1]]) #[[ATTR6]]
2382+
// CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt <2 x double> [[TMP0]], [[TMP1]]
2383+
// CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[CMP_I]], <2 x double> [[TMP1]], <2 x double> [[TMP0]]
23822384
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x double> [[TMP2]] to <4 x i32>
23832385
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
23842386
//

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -162,16 +162,6 @@ def int_wasm_q15mulr_sat_signed :
162162
[llvm_v8i16_ty, llvm_v8i16_ty],
163163
[IntrNoMem, IntrSpeculatable]>;
164164

165-
// TODO: Replace these intrinsics with normal ISel patterns
166-
def int_wasm_pmin :
167-
Intrinsic<[llvm_anyvector_ty],
168-
[LLVMMatchType<0>, LLVMMatchType<0>],
169-
[IntrNoMem, IntrSpeculatable]>;
170-
def int_wasm_pmax :
171-
Intrinsic<[llvm_anyvector_ty],
172-
[LLVMMatchType<0>, LLVMMatchType<0>],
173-
[IntrNoMem, IntrSpeculatable]>;
174-
175165
def int_wasm_extmul_low_signed :
176166
Intrinsic<[llvm_anyvector_ty],
177167
[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1122,10 +1122,32 @@ defm MIN : SIMDBinaryFP<fminimum, "min", 232>;
11221122
defm MAX : SIMDBinaryFP<fmaximum, "max", 233>;
11231123

11241124
// Pseudo-minimum: pmin
1125-
defm PMIN : SIMDBinaryFP<int_wasm_pmin, "pmin", 234>;
1125+
def pmin : PatFrag<(ops node:$lhs, node:$rhs),
1126+
(vselect (setolt $rhs, $lhs), $rhs, $lhs)>;
1127+
defm PMIN : SIMDBinaryFP<pmin, "pmin", 234>;
11261128

11271129
// Pseudo-maximum: pmax
1128-
defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>;
1130+
def pmax : PatFrag<(ops node:$lhs, node:$rhs),
1131+
(vselect (setolt $lhs, $rhs), $rhs, $lhs)>;
1132+
defm PMAX : SIMDBinaryFP<pmax, "pmax", 235>;
1133+
1134+
// Also match the pmin/pmax cases where the operands are int vectors (but the
1135+
// comparison is still a floating point comparison). This can happen when using
1136+
// the wasm_simd128.h intrinsics because v128_t is an integer vector.
1137+
foreach vec = [F32x4, F64x2] in {
1138+
defvar pmin = !cast<NI>("PMIN_"#vec);
1139+
defvar pmax = !cast<NI>("PMAX_"#vec);
1140+
def : Pat<(vec.int_vt (vselect
1141+
(setolt (vec.vt (bitconvert V128:$rhs)),
1142+
(vec.vt (bitconvert V128:$lhs))),
1143+
V128:$rhs, V128:$lhs)),
1144+
(pmin $lhs, $rhs)>;
1145+
def : Pat<(vec.int_vt (vselect
1146+
(setolt (vec.vt (bitconvert V128:$lhs)),
1147+
(vec.vt (bitconvert V128:$rhs))),
1148+
V128:$rhs, V128:$lhs)),
1149+
(pmax $lhs, $rhs)>;
1150+
}
11291151

11301152
//===----------------------------------------------------------------------===//
11311153
// Conversions

‎llvm/test/CodeGen/WebAssembly/simd-arith.ll

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1409,6 +1409,54 @@ define <4 x float> @max_const_intrinsic_v4f32() {
14091409
ret <4 x float> %a
14101410
}
14111411

1412+
; CHECK-LABEL: pmin_v4f32:
1413+
; NO-SIMD128-NOT: f32x4
1414+
; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
1415+
; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1416+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1417+
define <4 x float> @pmin_v4f32(<4 x float> %x, <4 x float> %y) {
1418+
%c = fcmp olt <4 x float> %y, %x
1419+
%a = select <4 x i1> %c, <4 x float> %y, <4 x float> %x
1420+
ret <4 x float> %a
1421+
}
1422+
1423+
; CHECK-LABEL: pmin_int_v4f32:
1424+
; NO-SIMD128-NOT: f32x4
1425+
; SIMD128-NEXT: .functype pmin_int_v4f32 (v128, v128) -> (v128){{$}}
1426+
; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1427+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1428+
define <4 x i32> @pmin_int_v4f32(<4 x i32> %x, <4 x i32> %y) {
1429+
%fx = bitcast <4 x i32> %x to <4 x float>
1430+
%fy = bitcast <4 x i32> %y to <4 x float>
1431+
%c = fcmp olt <4 x float> %fy, %fx
1432+
%a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %x
1433+
ret <4 x i32> %a
1434+
}
1435+
1436+
; CHECK-LABEL: pmax_v4f32:
1437+
; NO-SIMD128-NOT: f32x4
1438+
; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
1439+
; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1440+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1441+
define <4 x float> @pmax_v4f32(<4 x float> %x, <4 x float> %y) {
1442+
%c = fcmp olt <4 x float> %x, %y
1443+
%a = select <4 x i1> %c, <4 x float> %y, <4 x float> %x
1444+
ret <4 x float> %a
1445+
}
1446+
1447+
; CHECK-LABEL: pmax_int_v4f32:
1448+
; NO-SIMD128-NOT: f32x4
1449+
; SIMD128-NEXT: .functype pmax_int_v4f32 (v128, v128) -> (v128){{$}}
1450+
; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1451+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1452+
define <4 x i32> @pmax_int_v4f32(<4 x i32> %x, <4 x i32> %y) {
1453+
%fx = bitcast <4 x i32> %x to <4 x float>
1454+
%fy = bitcast <4 x i32> %y to <4 x float>
1455+
%c = fcmp olt <4 x float> %fx, %fy
1456+
%a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %x
1457+
ret <4 x i32> %a
1458+
}
1459+
14121460
; CHECK-LABEL: add_v4f32:
14131461
; NO-SIMD128-NOT: f32x4
14141462
; SIMD128-NEXT: .functype add_v4f32 (v128, v128) -> (v128){{$}}
@@ -1585,6 +1633,54 @@ define <2 x double> @max_const_intrinsic_v2f64() {
15851633
ret <2 x double> %a
15861634
}
15871635

1636+
; CHECK-LABEL: pmin_v2f64:
1637+
; NO-SIMD128-NOT: f64x2
1638+
; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
1639+
; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1640+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1641+
define <2 x double> @pmin_v2f64(<2 x double> %x, <2 x double> %y) {
1642+
%c = fcmp olt <2 x double> %y, %x
1643+
%a = select <2 x i1> %c, <2 x double> %y, <2 x double> %x
1644+
ret <2 x double> %a
1645+
}
1646+
1647+
; CHECK-LABEL: pmin_int_v2f64:
1648+
; NO-SIMD128-NOT: f64x2
1649+
; SIMD128-NEXT: .functype pmin_int_v2f64 (v128, v128) -> (v128){{$}}
1650+
; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1651+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1652+
define <2 x i64> @pmin_int_v2f64(<2 x i64> %x, <2 x i64> %y) {
1653+
%fx = bitcast <2 x i64> %x to <2 x double>
1654+
%fy = bitcast <2 x i64> %y to <2 x double>
1655+
%c = fcmp olt <2 x double> %fy, %fx
1656+
%a = select <2 x i1> %c, <2 x i64> %y, <2 x i64> %x
1657+
ret <2 x i64> %a
1658+
}
1659+
1660+
; CHECK-LABEL: pmax_v2f64:
1661+
; NO-SIMD128-NOT: f64x2
1662+
; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
1663+
; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1664+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1665+
define <2 x double> @pmax_v2f64(<2 x double> %x, <2 x double> %y) {
1666+
%c = fcmp olt <2 x double> %x, %y
1667+
%a = select <2 x i1> %c, <2 x double> %y, <2 x double> %x
1668+
ret <2 x double> %a
1669+
}
1670+
1671+
; CHECK-LABEL: pmax_int_v2f64:
1672+
; NO-SIMD128-NOT: f64x2
1673+
; SIMD128-NEXT: .functype pmax_int_v2f64 (v128, v128) -> (v128){{$}}
1674+
; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1675+
; SIMD128-NEXT: return $pop[[R]]{{$}}
1676+
define <2 x i64> @pmax_int_v2f64(<2 x i64> %x, <2 x i64> %y) {
1677+
%fx = bitcast <2 x i64> %x to <2 x double>
1678+
%fy = bitcast <2 x i64> %y to <2 x double>
1679+
%c = fcmp olt <2 x double> %fx, %fy
1680+
%a = select <2 x i1> %c, <2 x i64> %y, <2 x i64> %x
1681+
ret <2 x i64> %a
1682+
}
1683+
15881684
; CHECK-LABEL: add_v2f64:
15891685
; NO-SIMD128-NOT: f64x2
15901686
; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}}

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Lines changed: 0 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -685,26 +685,6 @@ define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float
685685
ret <4 x float> %a
686686
}
687687

688-
; CHECK-LABEL: pmin_v4f32:
689-
; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
690-
; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
691-
; CHECK-NEXT: return $pop[[R]]{{$}}
692-
declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>)
693-
define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) {
694-
%v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b)
695-
ret <4 x float> %v
696-
}
697-
698-
; CHECK-LABEL: pmax_v4f32:
699-
; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
700-
; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
701-
; CHECK-NEXT: return $pop[[R]]{{$}}
702-
declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>)
703-
define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) {
704-
%v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b)
705-
ret <4 x float> %v
706-
}
707-
708688
; CHECK-LABEL: ceil_v4f32:
709689
; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}}
710690
; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}}
@@ -760,26 +740,6 @@ define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x do
760740
ret <2 x double> %a
761741
}
762742

763-
; CHECK-LABEL: pmin_v2f64:
764-
; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
765-
; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
766-
; CHECK-NEXT: return $pop[[R]]{{$}}
767-
declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>)
768-
define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) {
769-
%v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b)
770-
ret <2 x double> %v
771-
}
772-
773-
; CHECK-LABEL: pmax_v2f64:
774-
; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
775-
; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
776-
; CHECK-NEXT: return $pop[[R]]{{$}}
777-
declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>)
778-
define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) {
779-
%v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b)
780-
ret <2 x double> %v
781-
}
782-
783743
; CHECK-LABEL: ceil_v2f64:
784744
; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}}
785745
; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}}

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