@@ -1128,6 +1128,21 @@ impl InlineAsmClobberAbi {
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} ,
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InlineAsmClobberAbi :: PowerPC => clobbered_regs ! {
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PowerPC PowerPCInlineAsmReg {
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+ // Refs:
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+ // - PPC32 SysV: "3.2. Function Calling Sequence" in Power Architecture® 32-bit Application Binary Interface Supplement 1.0 - Linux® & Embedded
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+ // https://web.archive.org/web/20120608163804/https://www.power.org/resources/downloads/Power-Arch-32-bit-ABI-supp-1.0-Unified.pdf
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+ // - PPC64 ELFv1: "3.2. Function Calling Sequence" in 64-bit PowerPC ELF Application Binary Interface Supplement 1.9
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+ // https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#FUNC-CALL
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+ // - PPC64 ELFv2: "2.2 Function Calling Sequence" in 64-Bit ELF V2 ABI Specification: Power Architecture, Revision 1.5
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+ // https://openpowerfoundation.org/specifications/64bitelfabi/
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+ // - AIX:
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+ // - Register usage and conventions
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+ // https://www.ibm.com/docs/en/aix/7.3?topic=overview-register-usage-conventions
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+ // - Special registers in the PowerPC®
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+ // https://www.ibm.com/docs/en/aix/7.3?topic=overview-special-registers-in-powerpc
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+ // - AIX vector programming
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+ // https://www.ibm.com/docs/en/aix/7.3?topic=concepts-aix-vector-programming
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+
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// r0, r3-r12
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r0,
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r3, r4, r5, r6, r7,
@@ -1138,8 +1153,6 @@ impl InlineAsmClobberAbi {
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f8, f9, f10, f11, f12, f13,
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// v0-v19
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- // FIXME: PPC32 SysV ABI does not mention vector registers processing.
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- // https://refspecs.linuxfoundation.org/elf/elfspec_ppc.pdf
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v0, v1, v2, v3, v4, v5, v6, v7,
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v8, v9, v10, v11, v12, v13, v14,
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v15, v16, v17, v18, v19,
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