@@ -1017,12 +1017,17 @@ impl f32 {
1017
1017
#[ unstable( feature = "num_midpoint" , issue = "110840" ) ]
1018
1018
pub fn midpoint ( self , other : f32 ) -> f32 {
1019
1019
cfg_if ! {
1020
- if #[ cfg( all( target_arch = "arm" , target_pointer_width = "32" ,
1021
- not( target_feature = "vfp2" ) ) ) ] {
1022
- // some 32-bit ARM architectures don't have native double-precision floats
1023
- // so fall back to a similar algorithm as in f64, but using f32
1024
- // This should only differ in the specific NaNs reported.
1025
-
1020
+ if #[ cfg( any(
1021
+ target_arch = "x86_64" ,
1022
+ target_arch = "aarch64" ,
1023
+ all( any( target_arch="riscv32" , target_arch= "riscv64" ) , target_feature="d" ) ,
1024
+ all( target_arch = "arm" , target_feature="vfp2" ) ,
1025
+ ) ) ] {
1026
+ // whitelist the faster implementation to targets that have known good 64-bit float
1027
+ // implementations. Falling back to the branchy code on targets that don't have
1028
+ // 64-bit hardware floats or buggy implementations.
1029
+ ( ( f64 :: from( self ) + f64 :: from( other) ) / 2.0 ) as f32
1030
+ } else {
1026
1031
const LO : f32 = f32 :: MIN_POSITIVE * 2. ;
1027
1032
const HI : f32 = f32 :: MAX / 2. ;
1028
1033
@@ -1043,8 +1048,6 @@ impl f32 {
1043
1048
// Not safe to halve a and b
1044
1049
( a / 2. ) + ( b / 2. )
1045
1050
}
1046
- } else {
1047
- ( ( f64 :: from( self ) + f64 :: from( other) ) / 2.0 ) as f32
1048
1051
}
1049
1052
}
1050
1053
}
0 commit comments