[Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

This patch adds the predicate-as-counter registers pn0-pn15 to the
list of supported registers used when writing inline assembly.

Tests added to

  clang/test/CodeGen/aarch64-sve-inline-asm.c

Differential Revision: https://reviews.llvm.org/D156115

Author: david-arm

clang/lib/Basic/Targets/AArch64.cpp

@@ -1164,7 +1164,11 @@ const char *const AArch64TargetInfo::GCCRegNames[] = {
 
     // SVE predicate registers
     "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
-    "p11", "p12", "p13", "p14", "p15"
+    "p11", "p12", "p13", "p14", "p15",
+
+    // SVE predicate-as-counter registers
+    "pn0",  "pn1",  "pn2",  "pn3",  "pn4",  "pn5",  "pn6",  "pn7",  "pn8",
+    "pn9",  "pn10", "pn11", "pn12", "pn13", "pn14", "pn15"
 };
 
 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {

clang/test/CodeGen/aarch64-sve-inline-asm.c

@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2p1 \
+// RUN:   -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2p1 \
+// RUN:   -S -o /dev/null
 
 void test_sve_asm(void) {
   asm volatile(
@@ -9,5 +13,16 @@ void test_sve_asm(void) {
       :
       :
       : "z0", "z31", "p0", "p15");
+  // CHECK-LABEL: @test_sve_asm
   // CHECK: "~{z0},~{z31},~{p0},~{p15}"
 }
+
+void test_sve2p1_asm(void) {
+  asm("pfalse pn0.b\n"
+      "ptrue pn8.d\n"
+      "ptrue pn15.b\n"
+      "pext p3.b, pn8[1]\n"
+      ::: "pn0", "pn8", "pn15", "p3");
+  // CHECK-LABEL: @test_sve2p1_asm
+  // CHECK: "~{pn0},~{pn8},~{pn15},~{p3}"
+}