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Merge pull request #53 from Amanieu/backport10
Port 2 commits from LLVM 9 branch to LLVM 10 branch
2 parents 6a831f0 + 756ba37 commit 887a77d

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5 files changed

+152
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5 files changed

+152
-4
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‎llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

+16-1
Original file line numberDiff line numberDiff line change
@@ -225,6 +225,21 @@ static bool isRegUsedByPhiNodes(unsigned DefReg,
225225
return false;
226226
}
227227

228+
static bool isTerminatingEHLabel(MachineBasicBlock *MBB, MachineInstr &MI) {
229+
// Ignore non-EH labels.
230+
if (!MI.isEHLabel())
231+
return false;
232+
233+
// Any EH label outside a landing pad must be for an invoke. Consider it a
234+
// terminator.
235+
if (!MBB->isEHPad())
236+
return true;
237+
238+
// If this is a landingpad, the first non-phi instruction will be an EH_LABEL.
239+
// Don't consider that label to be a terminator.
240+
return MI.getIterator() != MBB->getFirstNonPHI();
241+
}
242+
228243
/// Build a map of instruction orders. Return the first terminator and its
229244
/// order. Consider EH_LABEL instructions to be terminators as well, since local
230245
/// values for phis after invokes must be materialized before the call.
@@ -233,7 +248,7 @@ void FastISel::InstOrderMap::initialize(
233248
unsigned Order = 0;
234249
for (MachineInstr &I : *MBB) {
235250
if (!FirstTerminator &&
236-
(I.isTerminator() || (I.isEHLabel() && &I != &MBB->front()))) {
251+
(I.isTerminator() || isTerminatingEHLabel(MBB, I))) {
237252
FirstTerminator = &I;
238253
FirstTerminatorOrder = Order;
239254
}

‎llvm/lib/Target/X86/X86AsmPrinter.cpp

+45-1
Original file line numberDiff line numberDiff line change
@@ -404,7 +404,7 @@ void X86AsmPrinter::PrintIntelMemReference(const MachineInstr *MI,
404404
static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
405405
char Mode, raw_ostream &O) {
406406
Register Reg = MO.getReg();
407-
bool EmitPercent = true;
407+
bool EmitPercent = MO.getParent()->getInlineAsmDialect() == InlineAsm::AD_ATT;
408408

409409
if (!X86::GR8RegClass.contains(Reg) &&
410410
!X86::GR16RegClass.contains(Reg) &&
@@ -443,6 +443,42 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
443443
return false;
444444
}
445445

446+
static bool printAsmVRegister(X86AsmPrinter &P, const MachineOperand &MO,
447+
char Mode, raw_ostream &O) {
448+
unsigned Reg = MO.getReg();
449+
bool EmitPercent = MO.getParent()->getInlineAsmDialect() == InlineAsm::AD_ATT;
450+
451+
unsigned Index;
452+
if (X86::VR128XRegClass.contains(Reg))
453+
Index = Reg - X86::XMM0;
454+
else if (X86::VR256XRegClass.contains(Reg))
455+
Index = Reg - X86::YMM0;
456+
else if (X86::VR512RegClass.contains(Reg))
457+
Index = Reg - X86::ZMM0;
458+
else
459+
return true;
460+
461+
switch (Mode) {
462+
default: // Unknown mode.
463+
return true;
464+
case 'x': // Print V4SFmode register
465+
Reg = X86::XMM0 + Index;
466+
break;
467+
case 't': // Print V8SFmode register
468+
Reg = X86::YMM0 + Index;
469+
break;
470+
case 'g': // Print V16SFmode register
471+
Reg = X86::ZMM0 + Index;
472+
break;
473+
}
474+
475+
if (EmitPercent)
476+
O << '%';
477+
478+
O << X86ATTInstPrinter::getRegisterName(Reg);
479+
return false;
480+
}
481+
446482
/// PrintAsmOperand - Print out an operand for an inline asm expression.
447483
///
448484
bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
@@ -517,6 +553,14 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
517553
PrintOperand(MI, OpNo, O);
518554
return false;
519555

556+
case 'x': // Print V4SFmode register
557+
case 't': // Print V8SFmode register
558+
case 'g': // Print V16SFmode register
559+
if (MO.isReg())
560+
return printAsmVRegister(*this, MO, ExtraCode[0], O);
561+
PrintOperand(MI, OpNo, O);
562+
return false;
563+
520564
case 'P': // This is the operand of a call, treat specially.
521565
PrintPCRelImm(MI, OpNo, O);
522566
return false;

‎llvm/test/CodeGen/X86/asm-modifier2.ll

+53
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
; RUN: llc < %s | FileCheck %s
2+
3+
define void @test1() {
4+
; CHECK-LABEL: test1:
5+
; CHECK: vmovaps %xmm0, %xmm0
6+
; CHECK: vmovaps %ymm0, %ymm0
7+
; CHECK: vmovaps %zmm0, %zmm0
8+
tail call void asm sideeffect "vmovaps ${0:x}, ${0:x}", "{xmm0},~{dirflag},~{fpsr},~{flags}"(i32 0)
9+
tail call void asm sideeffect "vmovaps ${0:t}, ${0:t}", "{xmm0},~{dirflag},~{fpsr},~{flags}"(i32 0)
10+
tail call void asm sideeffect "vmovaps ${0:g}, ${0:g}", "{xmm0},~{dirflag},~{fpsr},~{flags}"(i32 0)
11+
ret void
12+
}
13+
14+
define void @test2() {
15+
; CHECK-LABEL: test2:
16+
; CHECK: vmovaps %xmm0, %xmm0
17+
; CHECK: vmovaps %ymm0, %ymm0
18+
; CHECK: vmovaps %zmm0, %zmm0
19+
tail call void asm sideeffect inteldialect "vmovaps ${0:x}, ${0:x}", "{xmm0},~{dirflag},~{fpsr},~{flags}"(i32 0)
20+
tail call void asm sideeffect inteldialect "vmovaps ${0:t}, ${0:t}", "{xmm0},~{dirflag},~{fpsr},~{flags}"(i32 0)
21+
tail call void asm sideeffect inteldialect "vmovaps ${0:g}, ${0:g}", "{xmm0},~{dirflag},~{fpsr},~{flags}"(i32 0)
22+
ret void
23+
}
24+
25+
define void @test3() {
26+
; CHECK-LABEL: test3:
27+
; CHECK: movb %al, %al
28+
; CHECK: movb %ah, %ah
29+
; CHECK: movw %ax, %ax
30+
; CHECK: movl %eax, %eax
31+
; CHECK: movq %rax, %rax
32+
tail call void asm sideeffect "mov ${0:b}, ${0:b}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
33+
tail call void asm sideeffect "mov ${0:h}, ${0:h}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
34+
tail call void asm sideeffect "mov ${0:w}, ${0:w}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
35+
tail call void asm sideeffect "mov ${0:k}, ${0:k}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
36+
tail call void asm sideeffect "mov ${0:q}, ${0:q}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
37+
ret void
38+
}
39+
40+
define void @test4() {
41+
; CHECK-LABEL: test4:
42+
; CHECK: movb %al, %al
43+
; CHECK: movb %ah, %ah
44+
; CHECK: movw %ax, %ax
45+
; CHECK: movl %eax, %eax
46+
; CHECK: movq %rax, %rax
47+
tail call void asm sideeffect inteldialect "mov ${0:b}, ${0:b}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
48+
tail call void asm sideeffect inteldialect "mov ${0:h}, ${0:h}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
49+
tail call void asm sideeffect inteldialect "mov ${0:w}, ${0:w}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
50+
tail call void asm sideeffect inteldialect "mov ${0:k}, ${0:k}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
51+
tail call void asm sideeffect inteldialect "mov ${0:q}, ${0:q}", "{eax},~{dirflag},~{fpsr},~{flags}"(i32 0)
52+
ret void
53+
}

‎llvm/test/CodeGen/X86/inline-asm-bad-modifier.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; RUN: not llc -mtriple=x86_64-- < %s 2>&1 | FileCheck %s
22

3-
;CHECK: error: invalid operand in inline asm: 'vmovd ${1:x}, $0'
3+
;CHECK: error: invalid operand in inline asm: 'vmovd ${1:k}, $0'
44
define i32 @foo() {
55
entry:
6-
%0 = tail call i32 asm sideeffect "vmovd ${1:x}, $0", "=r,x,~{dirflag},~{fpsr},~{flags}"(<2 x i64> <i64 240518168632, i64 240518168632>)
6+
%0 = tail call i32 asm sideeffect "vmovd ${1:k}, $0", "=r,x,~{dirflag},~{fpsr},~{flags}"(<2 x i64> <i64 240518168632, i64 240518168632>)
77
ret i32 %0
88
}

‎llvm/test/CodeGen/X86/sink-local-value.ll

+36
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,42 @@ try.cont: ; preds = %entry, %lpad
145145
; CHECK: retl
146146

147147

148+
define i32 @lpad_phi() personality i32 (...)* @__gxx_personality_v0 {
149+
entry:
150+
store i32 42, i32* @sink_across
151+
invoke void @may_throw()
152+
to label %try.cont unwind label %lpad
153+
154+
lpad: ; preds = %entry
155+
%p = phi i32 [ 11, %entry ] ; Trivial, but -O0 keeps it
156+
%0 = landingpad { i8*, i32 }
157+
catch i8* null
158+
store i32 %p, i32* @sink_across
159+
br label %try.cont
160+
161+
try.cont: ; preds = %entry, %lpad
162+
%r.0 = phi i32 [ 13, %entry ], [ 55, %lpad ]
163+
ret i32 %r.0
164+
}
165+
166+
; The constant materialization should be *after* the stores to sink_across, but
167+
; before any EH_LABEL.
168+
169+
; CHECK-LABEL: lpad_phi:
170+
; CHECK: movl $42, sink_across
171+
; CHECK: movl $13, %{{[a-z]*}}
172+
; CHECK: .Ltmp{{.*}}:
173+
; CHECK: calll may_throw
174+
; CHECK: .Ltmp{{.*}}:
175+
; CHECK: jmp .LBB{{.*}}
176+
; CHECK: .LBB{{.*}}: # %lpad
177+
; CHECK-NEXT: .Ltmp{{.*}}:
178+
; CHECK: movl {{.*}}, sink_across
179+
; CHECK: movl $55, %{{[a-z]*}}
180+
; CHECK: .LBB{{.*}}: # %try.cont
181+
; CHECK: retl
182+
183+
148184
; Function Attrs: nounwind readnone speculatable
149185
declare void @llvm.dbg.value(metadata, metadata, metadata) #0
150186

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