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Jessica Paquette
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[AArch64][GlobalISel] Legalize non-register-sized scalar G_BITREVERSE
Clamp types to [s32, s64] and make them a power of 2. This matches SDAG's behaviour. https://godbolt.org/z/vTeGqf4vT Differential Revision: https://reviews.llvm.org/D108344
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llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -630,7 +630,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lower();
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// TODO: Custom lowering for v2s32, v4s32, v2s64.
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getActionDefinitionsBuilder(G_BITREVERSE).legalFor({s32, s64, v8s8, v16s8});
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getActionDefinitionsBuilder(G_BITREVERSE)
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.legalFor({s32, s64, v8s8, v16s8})
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.widenScalarToNextPow2(0, /*Min = */ 32)
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.clampScalar(0, s32, s64);
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getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).lower();
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llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitreverse.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s32_legal
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; CHECK: liveins: $w0
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; CHECK: %copy:_(s32) = COPY $w0
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; CHECK: %bitreverse:_(s32) = G_BITREVERSE %copy
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; CHECK: $w0 = COPY %bitreverse(s32)
@@ -25,6 +26,7 @@ body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: s64_legal
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; CHECK: liveins: $x0
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; CHECK: %copy:_(s64) = COPY $x0
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; CHECK: %bitreverse:_(s64) = G_BITREVERSE %copy
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; CHECK: $x0 = COPY %bitreverse(s64)
@@ -41,6 +43,7 @@ body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: v8s8_legal
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; CHECK: liveins: $x0
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; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
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; CHECK: %bitreverse:_(<8 x s8>) = G_BITREVERSE %vec
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; CHECK: $x0 = COPY %bitreverse(<8 x s8>)
@@ -57,6 +60,7 @@ body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v16s8_legal
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; CHECK: liveins: $q0
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; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
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; CHECK: %bitreverse:_(<16 x s8>) = G_BITREVERSE %vec
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; CHECK: $q0 = COPY %bitreverse(<16 x s8>)
@@ -66,3 +70,66 @@ body: |
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$q0 = COPY %bitreverse
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RET_ReallyLR implicit $q0
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...
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---
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name: s8_widen
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $b0
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; CHECK-LABEL: name: s8_widen
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; CHECK: liveins: $b0
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; CHECK: %copy:_(s8) = COPY $b0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %copy(s8)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[ANYEXT]]
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s64)
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; CHECK: %bitreverse:_(s8) = G_TRUNC [[LSHR]](s32)
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; CHECK: $b0 = COPY %bitreverse(s8)
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; CHECK: RET_ReallyLR implicit $b0
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%copy:_(s8) = COPY $b0
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%bitreverse:_(s8) = G_BITREVERSE %copy
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$b0 = COPY %bitreverse
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RET_ReallyLR implicit $b0
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...
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---
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name: s3_widen
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $b0
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; CHECK-LABEL: name: s3_widen
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; CHECK: liveins: $b0
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; CHECK: %copy:_(s8) = COPY $b0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %copy(s8)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[ANYEXT]]
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 29
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s64)
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; CHECK: %ext:_(s8) = G_TRUNC [[LSHR]](s32)
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; CHECK: $b0 = COPY %ext(s8)
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; CHECK: RET_ReallyLR implicit $b0
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%copy:_(s8) = COPY $b0
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%trunc:_(s3) = G_TRUNC %copy
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%bitreverse:_(s3) = G_BITREVERSE %trunc
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%ext:_(s8) = G_ANYEXT %bitreverse
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$b0 = COPY %ext
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RET_ReallyLR implicit $b0
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...
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---
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name: s128_narrow
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: s128_narrow
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; CHECK: liveins: $q0
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; CHECK: %copy:_(s128) = COPY $q0
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy(s128)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV1]]
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV]]
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; CHECK: %bitreverse:_(s128) = G_MERGE_VALUES [[BITREVERSE]](s64), [[BITREVERSE1]](s64)
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; CHECK: $q0 = COPY %bitreverse(s128)
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; CHECK: RET_ReallyLR implicit $q0
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%copy:_(s128) = COPY $q0
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%bitreverse:_(s128) = G_BITREVERSE %copy
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$q0 = COPY %bitreverse
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RET_ReallyLR implicit $q0

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