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[WebAssembly] Implement i64x2 comparisons (#98)
Removes the prototype builtin and intrinsic for i64x2.eq and implements that instruction as well as the other i64x2 comparison instructions in the final SIMD spec. Unsigned comparisons were not included in the final spec, so they still need to be scalarized via a custom lowering. Differential Revision: https://reviews.llvm.org/D99623 Co-authored-by: Thomas Lively <[email protected]>
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clang/include/clang/Basic/BuiltinsWebAssembly.def

-2
Original file line numberDiff line numberDiff line change
@@ -215,7 +215,5 @@ TARGET_BUILTIN(__builtin_wasm_store16_lane, "vs*V8sIi", "n", "simd128")
215215
TARGET_BUILTIN(__builtin_wasm_store32_lane, "vi*V4iIi", "n", "simd128")
216216
TARGET_BUILTIN(__builtin_wasm_store64_lane, "vLLi*V2LLiIi", "n", "simd128")
217217

218-
TARGET_BUILTIN(__builtin_wasm_eq_i64x2, "V2LLiV2LLiV2LLi", "nc", "simd128")
219-
220218
#undef BUILTIN
221219
#undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

-6
Original file line numberDiff line numberDiff line change
@@ -17085,12 +17085,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1708517085
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_popcnt);
1708617086
return Builder.CreateCall(Callee, {Vec});
1708717087
}
17088-
case WebAssembly::BI__builtin_wasm_eq_i64x2: {
17089-
Value *LHS = EmitScalarExpr(E->getArg(0));
17090-
Value *RHS = EmitScalarExpr(E->getArg(1));
17091-
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_eq);
17092-
return Builder.CreateCall(Callee, {LHS, RHS});
17093-
}
1709417088
case WebAssembly::BI__builtin_wasm_any_true_i8x16:
1709517089
case WebAssembly::BI__builtin_wasm_any_true_i16x8:
1709617090
case WebAssembly::BI__builtin_wasm_any_true_i32x4:

clang/test/CodeGen/builtins-wasm.c

-6
Original file line numberDiff line numberDiff line change
@@ -650,12 +650,6 @@ i8x16 popcnt(i8x16 x) {
650650
// WEBASSEMBLY-NEXT: ret
651651
}
652652

653-
i64x2 eq_i64x2(i64x2 x, i64x2 y) {
654-
return __builtin_wasm_eq_i64x2(x, y);
655-
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
656-
// WEBASSEMBLY-NEXT: ret
657-
}
658-
659653
int any_true_i8x16(i8x16 x) {
660654
return __builtin_wasm_any_true_i8x16(x);
661655
// WEBASSEMBLY: call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

-7
Original file line numberDiff line numberDiff line change
@@ -294,13 +294,6 @@ def int_wasm_extadd_pairwise_unsigned :
294294
[LLVMSubdivide2VectorType<0>],
295295
[IntrNoMem, IntrSpeculatable]>;
296296

297-
// TODO: Remove this intrinsic and the associated builtin if i64x2.eq gets
298-
// merged to the proposal.
299-
def int_wasm_eq :
300-
Intrinsic<[llvm_v2i64_ty],
301-
[llvm_v2i64_ty, llvm_v2i64_ty],
302-
[IntrNoMem, IntrSpeculatable]>;
303-
304297
// TODO: Remove these if possible if they are merged to the spec.
305298
def int_wasm_convert_low_signed :
306299
Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

+5-8
Original file line numberDiff line numberDiff line change
@@ -186,9 +186,9 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
186186
for (auto T : {MVT::v4f32, MVT::v2f64})
187187
setOperationAction(Op, T, Expand);
188188

189-
// Expand operations not supported for i64x2 vectors
190-
for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)
191-
setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);
189+
// Unsigned comparison operations are unavailable for i64x2 vectors.
190+
for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE})
191+
setCondCodeAction(CC, MVT::v2i64, Custom);
192192

193193
// 64x2 conversions are not in the spec
194194
for (auto Op :
@@ -1775,11 +1775,8 @@ WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
17751775
SDValue WebAssemblyTargetLowering::LowerSETCC(SDValue Op,
17761776
SelectionDAG &DAG) const {
17771777
SDLoc DL(Op);
1778-
// The legalizer does not know how to expand the comparison modes of i64x2
1779-
// vectors because no comparison modes are supported. We could solve this by
1780-
// expanding all i64x2 SETCC nodes, but that seems to expand f64x2 SETCC nodes
1781-
// (which return i64x2 results) as well. So instead we manually unroll i64x2
1782-
// comparisons here.
1778+
// The legalizer does not know how to expand the unsupported comparison modes
1779+
// of i64x2 vectors, so we manually unroll them here.
17831780
assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);
17841781
SmallVector<SDValue, 2> LHS, RHS;
17851782
DAG.ExtractVectorElements(Op->getOperand(0), LHS);

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

+6-8
Original file line numberDiff line numberDiff line change
@@ -650,32 +650,38 @@ multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
650650
// Equality: eq
651651
let isCommutable = 1 in {
652652
defm EQ : SIMDConditionInt<"eq", SETEQ, 35>;
653+
defm EQ : SIMDCondition<I64x2, "eq", SETEQ, 214>;
653654
defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>;
654655
} // isCommutable = 1
655656

656657
// Non-equality: ne
657658
let isCommutable = 1 in {
658659
defm NE : SIMDConditionInt<"ne", SETNE, 36>;
660+
defm NE : SIMDCondition<I64x2, "ne", SETNE, 215>;
659661
defm NE : SIMDConditionFP<"ne", SETUNE, 66>;
660662
} // isCommutable = 1
661663

662664
// Less than: lt_s / lt_u / lt
663665
defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>;
666+
defm LT_S : SIMDCondition<I64x2, "lt_s", SETLT, 216>;
664667
defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>;
665668
defm LT : SIMDConditionFP<"lt", SETOLT, 67>;
666669

667670
// Greater than: gt_s / gt_u / gt
668671
defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>;
672+
defm GT_S : SIMDCondition<I64x2, "gt_s", SETGT, 217>;
669673
defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>;
670674
defm GT : SIMDConditionFP<"gt", SETOGT, 68>;
671675

672676
// Less than or equal: le_s / le_u / le
673677
defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>;
678+
defm LE_S : SIMDCondition<I64x2, "le_s", SETLE, 218>;
674679
defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>;
675680
defm LE : SIMDConditionFP<"le", SETOLE, 69>;
676681

677682
// Greater than or equal: ge_s / ge_u / ge
678683
defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>;
684+
defm GE_S : SIMDCondition<I64x2, "ge_s", SETGE, 219>;
679685
defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>;
680686
defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
681687

@@ -692,14 +698,6 @@ foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2],
692698
def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
693699
(nodes[1] $lhs, $rhs)>;
694700

695-
// Prototype i64x2.eq
696-
defm EQ_v2i64 :
697-
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
698-
[(set (v2i64 V128:$dst),
699-
(int_wasm_eq (v2i64 V128:$lhs), (v2i64 V128:$rhs)))],
700-
"i64x2.eq\t$dst, $lhs, $rhs", "i64x2.eq", 192>;
701-
702-
703701
//===----------------------------------------------------------------------===//
704702
// Bitwise operations
705703
//===----------------------------------------------------------------------===//

llvm/test/CodeGen/WebAssembly/simd-comparisons.ll

+44
Original file line numberDiff line numberDiff line change
@@ -637,44 +637,62 @@ define <4 x i32> @compare_sext_uge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
637637
}
638638

639639
; CHECK-LABEL: compare_eq_v2i64:
640+
; NO-SIMD128-NOT: i64x2
640641
; SIMD128-NEXT: .functype compare_eq_v2i64 (v128, v128) -> (v128){{$}}
642+
; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
643+
; SIMD128-NEXT: return $pop[[R]]{{$}}
641644
define <2 x i1> @compare_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {
642645
%res = icmp eq <2 x i64> %x, %y
643646
ret <2 x i1> %res
644647
}
645648

646649
; CHECK-LABEL: compare_sext_eq_v2i64:
650+
; NO-SIMD128-NOT: i64x2
647651
; SIMD128-NEXT: .functype compare_sext_eq_v2i64 (v128, v128) -> (v128){{$}}
652+
; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
653+
; SIMD128-NEXT: return $pop[[R]]{{$}}
648654
define <2 x i64> @compare_sext_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {
649655
%cmp = icmp eq <2 x i64> %x, %y
650656
%res = sext <2 x i1> %cmp to <2 x i64>
651657
ret <2 x i64> %res
652658
}
653659

654660
; CHECK-LABEL: compare_ne_v2i64:
661+
; NO-SIMD128-NOT: i64x2
655662
; SIMD128-NEXT: .functype compare_ne_v2i64 (v128, v128) -> (v128){{$}}
663+
; SIMD128-NEXT: i64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
664+
; SIMD128-NEXT: return $pop[[R]]{{$}}
656665
define <2 x i1> @compare_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {
657666
%res = icmp ne <2 x i64> %x, %y
658667
ret <2 x i1> %res
659668
}
660669

661670
; CHECK-LABEL: compare_sext_ne_v2i64:
671+
; NO-SIMD128-NOT: i64x2
662672
; SIMD128-NEXT: .functype compare_sext_ne_v2i64 (v128, v128) -> (v128){{$}}
673+
; SIMD128-NEXT: i64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
674+
; SIMD128-NEXT: return $pop[[R]]{{$}}
663675
define <2 x i64> @compare_sext_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {
664676
%cmp = icmp ne <2 x i64> %x, %y
665677
%res = sext <2 x i1> %cmp to <2 x i64>
666678
ret <2 x i64> %res
667679
}
668680

669681
; CHECK-LABEL: compare_slt_v2i64:
682+
; NO-SIMD128-NOT: i64x2
670683
; SIMD128-NEXT: .functype compare_slt_v2i64 (v128, v128) -> (v128){{$}}
684+
; SIMD128-NEXT: i64x2.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
685+
; SIMD128-NEXT: return $pop[[R]]{{$}}
671686
define <2 x i1> @compare_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
672687
%res = icmp slt <2 x i64> %x, %y
673688
ret <2 x i1> %res
674689
}
675690

676691
; CHECK-LABEL: compare_sext_slt_v2i64:
692+
; NO-SIMD128-NOT: i64x2
677693
; SIMD128-NEXT: .functype compare_sext_slt_v2i64 (v128, v128) -> (v128){{$}}
694+
; SIMD128-NEXT: i64x2.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
695+
; SIMD128-NEXT: return $pop[[R]]{{$}}
678696
define <2 x i64> @compare_sext_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
679697
%cmp = icmp slt <2 x i64> %x, %y
680698
%res = sext <2 x i1> %cmp to <2 x i64>
@@ -683,28 +701,36 @@ define <2 x i64> @compare_sext_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
683701

684702
; CHECK-LABEL: compare_ult_v2i64:
685703
; SIMD128-NEXT: .functype compare_ult_v2i64 (v128, v128) -> (v128){{$}}
704+
; SIMD128: i64.lt_u
686705
define <2 x i1> @compare_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {
687706
%res = icmp ult <2 x i64> %x, %y
688707
ret <2 x i1> %res
689708
}
690709

691710
; CHECK-LABEL: compare_sext_ult_v2i64:
692711
; SIMD128-NEXT: .functype compare_sext_ult_v2i64 (v128, v128) -> (v128){{$}}
712+
; SIMD128: i64.lt_u
693713
define <2 x i64> @compare_sext_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {
694714
%cmp = icmp ult <2 x i64> %x, %y
695715
%res = sext <2 x i1> %cmp to <2 x i64>
696716
ret <2 x i64> %res
697717
}
698718

699719
; CHECK-LABEL: compare_sle_v2i64:
720+
; NO-SIMD128-NOT: i64x2
700721
; SIMD128-NEXT: .functype compare_sle_v2i64 (v128, v128) -> (v128){{$}}
722+
; SIMD128-NEXT: i64x2.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
723+
; SIMD128-NEXT: return $pop[[R]]{{$}}
701724
define <2 x i1> @compare_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {
702725
%res = icmp sle <2 x i64> %x, %y
703726
ret <2 x i1> %res
704727
}
705728

706729
; CHECK-LABEL: compare_sext_sle_v2i64:
730+
; NO-SIMD128-NOT: i64x2
707731
; SIMD128-NEXT: .functype compare_sext_sle_v2i64 (v128, v128) -> (v128){{$}}
732+
; SIMD128-NEXT: i64x2.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
733+
; SIMD128-NEXT: return $pop[[R]]{{$}}
708734
define <2 x i64> @compare_sext_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {
709735
%cmp = icmp sle <2 x i64> %x, %y
710736
%res = sext <2 x i1> %cmp to <2 x i64>
@@ -713,28 +739,36 @@ define <2 x i64> @compare_sext_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {
713739

714740
; CHECK-LABEL: compare_ule_v2i64:
715741
; SIMD128-NEXT: .functype compare_ule_v2i64 (v128, v128) -> (v128){{$}}
742+
; SIMD128: i64.le_u
716743
define <2 x i1> @compare_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {
717744
%res = icmp ule <2 x i64> %x, %y
718745
ret <2 x i1> %res
719746
}
720747

721748
; CHECK-LABEL: compare_sext_ule_v2i64:
722749
; SIMD128-NEXT: .functype compare_sext_ule_v2i64 (v128, v128) -> (v128){{$}}
750+
; SIMD128: i64.le_u
723751
define <2 x i64> @compare_sext_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {
724752
%cmp = icmp ule <2 x i64> %x, %y
725753
%res = sext <2 x i1> %cmp to <2 x i64>
726754
ret <2 x i64> %res
727755
}
728756

729757
; CHECK-LABEL: compare_sgt_v2i64:
758+
; NO-SIMD128-NOT: i64x2
730759
; SIMD128-NEXT: .functype compare_sgt_v2i64 (v128, v128) -> (v128){{$}}
760+
; SIMD128-NEXT: i64x2.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
761+
; SIMD128-NEXT: return $pop[[R]]{{$}}
731762
define <2 x i1> @compare_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
732763
%res = icmp sgt <2 x i64> %x, %y
733764
ret <2 x i1> %res
734765
}
735766

736767
; CHECK-LABEL: compare_sext_sgt_v2i64:
768+
; NO-SIMD128-NOT: i64x2
737769
; SIMD128-NEXT: .functype compare_sext_sgt_v2i64 (v128, v128) -> (v128){{$}}
770+
; SIMD128-NEXT: i64x2.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
771+
; SIMD128-NEXT: return $pop[[R]]{{$}}
738772
define <2 x i64> @compare_sext_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
739773
%cmp = icmp sgt <2 x i64> %x, %y
740774
%res = sext <2 x i1> %cmp to <2 x i64>
@@ -743,28 +777,36 @@ define <2 x i64> @compare_sext_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
743777

744778
; CHECK-LABEL: compare_ugt_v2i64:
745779
; SIMD128-NEXT: .functype compare_ugt_v2i64 (v128, v128) -> (v128){{$}}
780+
; SIMD128: i64.gt_u
746781
define <2 x i1> @compare_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
747782
%res = icmp ugt <2 x i64> %x, %y
748783
ret <2 x i1> %res
749784
}
750785

751786
; CHECK-LABEL: compare_sext_ugt_v2i64:
752787
; SIMD128-NEXT: .functype compare_sext_ugt_v2i64 (v128, v128) -> (v128){{$}}
788+
; SIMD128: i64.gt_u
753789
define <2 x i64> @compare_sext_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
754790
%cmp = icmp ugt <2 x i64> %x, %y
755791
%res = sext <2 x i1> %cmp to <2 x i64>
756792
ret <2 x i64> %res
757793
}
758794

759795
; CHECK-LABEL: compare_sge_v2i64:
796+
; NO-SIMD128-NOT: i64x2
760797
; SIMD128-NEXT: .functype compare_sge_v2i64 (v128, v128) -> (v128){{$}}
798+
; SIMD128-NEXT: i64x2.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
799+
; SIMD128-NEXT: return $pop[[R]]{{$}}
761800
define <2 x i1> @compare_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
762801
%res = icmp sge <2 x i64> %x, %y
763802
ret <2 x i1> %res
764803
}
765804

766805
; CHECK-LABEL: compare_sext_sge_v2i64:
806+
; NO-SIMD128-NOT: i64x2
767807
; SIMD128-NEXT: .functype compare_sext_sge_v2i64 (v128, v128) -> (v128){{$}}
808+
; SIMD128-NEXT: i64x2.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
809+
; SIMD128-NEXT: return $pop[[R]]{{$}}
768810
define <2 x i64> @compare_sext_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
769811
%cmp = icmp sge <2 x i64> %x, %y
770812
%res = sext <2 x i1> %cmp to <2 x i64>
@@ -773,13 +815,15 @@ define <2 x i64> @compare_sext_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
773815

774816
; CHECK-LABEL: compare_uge_v2i64:
775817
; SIMD128-NEXT: .functype compare_uge_v2i64 (v128, v128) -> (v128){{$}}
818+
; SIMD128: i64.ge_u
776819
define <2 x i1> @compare_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
777820
%res = icmp uge <2 x i64> %x, %y
778821
ret <2 x i1> %res
779822
}
780823

781824
; CHECK-LABEL: compare_sext_uge_v2i64:
782825
; SIMD128-NEXT: .functype compare_sext_uge_v2i64 (v128, v128) -> (v128){{$}}
826+
; SIMD128: i64.ge_u
783827
define <2 x i64> @compare_sext_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
784828
%cmp = icmp uge <2 x i64> %x, %y
785829
%res = sext <2 x i1> %cmp to <2 x i64>

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

-10
Original file line numberDiff line numberDiff line change
@@ -553,16 +553,6 @@ define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
553553
; ==============================================================================
554554
; 2 x i64
555555
; ==============================================================================
556-
; CHECK-LABEL: eq_v2i64:
557-
; CHECK-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
558-
; CHECK-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
559-
; CHECK-NEXT: return $pop[[R]]{{$}}
560-
declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>)
561-
define <2 x i64> @eq_v2i64(<2 x i64> %x, <2 x i64> %y) {
562-
%a = call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
563-
ret <2 x i64> %a
564-
}
565-
566556
; CHECK-LABEL: extend_low_s_v2i64:
567557
; CHECK-NEXT: .functype extend_low_s_v2i64 (v128) -> (v128){{$}}
568558
; CHECK-NEXT: i64x2.extend_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}

llvm/test/CodeGen/WebAssembly/simd-select.ll

+2-18
Original file line numberDiff line numberDiff line change
@@ -299,33 +299,17 @@ define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
299299
ret <2 x i64> %res
300300
}
301301

302-
define <2 x i64> @vselect_cmp_v2i64(<2 x i64> %a, <2 x i64> %b,
302+
define <2 x i64> @vselect_cmp_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %x, <2 x i64> %y) {
303303
; CHECK-LABEL: vselect_cmp_v2i64:
304304
; CHECK: .functype vselect_cmp_v2i64 (v128, v128, v128, v128) -> (v128)
305305
; CHECK-NEXT: # %bb.0:
306306
; CHECK-NEXT: local.get 2
307307
; CHECK-NEXT: local.get 3
308-
; CHECK-NEXT: i64.const -1
309-
; CHECK-NEXT: i64.const 0
310308
; CHECK-NEXT: local.get 0
311-
; CHECK-NEXT: i64x2.extract_lane 0
312309
; CHECK-NEXT: local.get 1
313-
; CHECK-NEXT: i64x2.extract_lane 0
314-
; CHECK-NEXT: i64.lt_s
315-
; CHECK-NEXT: i64.select
316-
; CHECK-NEXT: i64x2.splat
317-
; CHECK-NEXT: i64.const -1
318-
; CHECK-NEXT: i64.const 0
319-
; CHECK-NEXT: local.get 0
320-
; CHECK-NEXT: i64x2.extract_lane 1
321-
; CHECK-NEXT: local.get 1
322-
; CHECK-NEXT: i64x2.extract_lane 1
323-
; CHECK-NEXT: i64.lt_s
324-
; CHECK-NEXT: i64.select
325-
; CHECK-NEXT: i64x2.replace_lane 1
310+
; CHECK-NEXT: i64x2.lt_s
326311
; CHECK-NEXT: v128.bitselect
327312
; CHECK-NEXT: # fallthrough-return
328-
<2 x i64> %x, <2 x i64> %y) {
329313
%c = icmp slt <2 x i64> %a, %b
330314
%res = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %y
331315
ret <2 x i64> %res

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