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[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst

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‎llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst

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‎llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst

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‎llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst

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‎llvm/docs/AMDGPU/gfx10_addr_buf.rst

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* *
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* Automatically generated file, do not edit! *
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* *
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.. _amdgpu_synid10_addr_buf:
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vaddr
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===========================
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This is an optional operand which may specify offset and/or index.
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*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
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* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
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* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
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* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
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* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
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*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

‎llvm/docs/AMDGPU/gfx10_addr_ds.rst

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* *
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* *
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.. _amdgpu_synid10_addr_ds:
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vaddr
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===========================
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An offset from the start of GDS/LDS memory.
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_addr_flat.rst

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* *
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* *
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.. _amdgpu_synid10_addr_flat:
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vaddr
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===========================
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A 64-bit flat address.
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*Size:* 2 dwords.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_addr_mimg.rst

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* *
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* *
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.. _amdgpu_synid10_addr_mimg:
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vaddr
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===========================
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Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
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This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
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*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
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* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
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* If specified using :ref:`standard VGPR syntax<amdgpu_synid_vcc_lo>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_attr.rst

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* *
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* *
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.. _amdgpu_synid10_attr:
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attr
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===========================
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Interpolation attribute and channel:
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============== ===================================
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Syntax Description
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============== ===================================
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attr{0..32}.x Attribute 0..32 with *x* channel.
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attr{0..32}.y Attribute 0..32 with *y* channel.
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attr{0..32}.z Attribute 0..32 with *z* channel.
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attr{0..32}.w Attribute 0..32 with *w* channel.
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============== ===================================
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Examples:
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.. parsed-literal::
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v_interp_p1_f32 v1, v0, attr0.x
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v_interp_p1_f32 v1, v0, attr32.w
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‎llvm/docs/AMDGPU/gfx10_base_smem_addr.rst

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* *
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.. _amdgpu_synid10_base_smem_addr:
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sbase
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===========================
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A 64-bit base address for scalar memory operations.
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*Size:* 2 dwords.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx10_base_smem_buf.rst

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* *
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* *
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.. _amdgpu_synid10_base_smem_buf:
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sbase
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===========================
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A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
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*Size:* 4 dwords.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst

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* *
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* *
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.. _amdgpu_synid10_base_smem_scratch:
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sbase
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===========================
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This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
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*Size:* 2 dwords.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`

‎llvm/docs/AMDGPU/gfx10_bimm16.rst

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* *
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* *
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.. _amdgpu_synid10_bimm16:
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imm16
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===========================
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An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
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‎llvm/docs/AMDGPU/gfx10_bimm32.rst

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.. _amdgpu_synid10_bimm32:
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imm32
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===========================
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An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
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‎llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst

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.. _amdgpu_synid10_data_buf_atomic128:
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vdata
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===========================
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst

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.. _amdgpu_synid10_data_buf_atomic32:
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vdata
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===========================
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst

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.. _amdgpu_synid10_data_buf_atomic64:
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vdata
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===========================
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst

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* *
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.. _amdgpu_synid10_data_mimg_atomic_cmp:
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vdata
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===========================
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
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* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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Note. The surface data format is indicated in the image resource constant but not in the instruction.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst

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* *
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.. _amdgpu_synid10_data_mimg_atomic_reg:
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vdata
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===========================
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
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* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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Note. The surface data format is indicated in the image resource constant but not in the instruction.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_mimg_store.rst

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* *
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.. _amdgpu_synid10_data_mimg_store:
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vdata
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===========================
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Image data to store by an *image_store* instruction.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst

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.. _amdgpu_synid10_data_mimg_store_d16:
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vdata
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===========================
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Image data to store by an *image_store* instruction.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
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* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
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*Operands:* :ref:`v<amdgpu_synid_v>`

‎llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst

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.. _amdgpu_synid10_data_smem_atomic128:
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sdata
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===========================
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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*Size:* 4 dwords.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

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