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Merging r354733:
------------------------------------------------------------------------ r354733 | nikic | 2019-02-23 19:59:01 +0100 (Sat, 23 Feb 2019) | 10 lines [WebAssembly] Fix select of and (PR40805) Fixes https://bugs.llvm.org/show_bug.cgi?id=40805 introduced by patterns added in D53676. I'm removing the patterns entirely here, as they are not correct in the general case. If necessary something more specific can be added in the future. Differential Revision: https://reviews.llvm.org/D58575 ------------------------------------------------------------------------ llvm-svn: 354860
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -122,10 +122,3 @@ def : Pat<(select (i32 (seteq I32:$cond, 0)), I32:$lhs, I32:$rhs),
122122
(SELECT_I32 I32:$rhs, I32:$lhs, I32:$cond)>;
123123
def : Pat<(select (i32 (seteq I32:$cond, 0)), I64:$lhs, I64:$rhs),
124124
(SELECT_I64 I64:$rhs, I64:$lhs, I32:$cond)>;
125-
126-
// The legalizer inserts an unnecessary `and 1` to make input conform
127-
// to getBooleanContents, which we can lower away.
128-
def : Pat<(select (i32 (and I32:$cond, 1)), I32:$lhs, I32:$rhs),
129-
(SELECT_I32 I32:$lhs, I32:$rhs, I32:$cond)>;
130-
def : Pat<(select (i32 (and I32:$cond, 1)), I64:$lhs, I64:$rhs),
131-
(SELECT_I64 I64:$lhs, I64:$rhs, I32:$cond)>;

‎llvm/test/CodeGen/WebAssembly/select.ll

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,10 @@ define i32 @select_i32_bool(i1 zeroext %a, i32 %b, i32 %c) {
1717

1818
; CHECK-LABEL: select_i32_bool_nozext:
1919
; CHECK-NEXT: .functype select_i32_bool_nozext (i32, i32, i32) -> (i32){{$}}
20-
; SLOW-NEXT: i32.select $push0=, $1, $2, $0{{$}}
21-
; SLOW-NEXT: return $pop0{{$}}
20+
; SLOW-NEXT: i32.const $push0=, 1{{$}}
21+
; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
22+
; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
23+
; SLOW-NEXT: return $pop2{{$}}
2224
define i32 @select_i32_bool_nozext(i1 %a, i32 %b, i32 %c) {
2325
%cond = select i1 %a, i32 %b, i32 %c
2426
ret i32 %cond
@@ -55,8 +57,10 @@ define i64 @select_i64_bool(i1 zeroext %a, i64 %b, i64 %c) {
5557

5658
; CHECK-LABEL: select_i64_bool_nozext:
5759
; CHECK-NEXT: .functype select_i64_bool_nozext (i32, i64, i64) -> (i64){{$}}
58-
; SLOW-NEXT: i64.select $push0=, $1, $2, $0{{$}}
59-
; SLOW-NEXT: return $pop0{{$}}
60+
; SLOW-NEXT: i32.const $push0=, 1{{$}}
61+
; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
62+
; SLOW-NEXT: i64.select $push2=, $1, $2, $pop1{{$}}
63+
; SLOW-NEXT: return $pop2{{$}}
6064
define i64 @select_i64_bool_nozext(i1 %a, i64 %b, i64 %c) {
6165
%cond = select i1 %a, i64 %b, i64 %c
6266
ret i64 %cond
@@ -157,3 +161,16 @@ define double @select_f64_ne(i32 %a, double %b, double %c) {
157161
%cond = select i1 %cmp, double %b, double %c
158162
ret double %cond
159163
}
164+
165+
; CHECK-LABEL: pr40805:
166+
; CHECK-NEXT: .functype pr40805 (i32, i32, i32) -> (i32){{$}}
167+
; SLOW-NEXT: i32.const $push0=, 1{{$}}
168+
; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
169+
; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
170+
; SLOW-NEXT: return $pop2{{$}}
171+
define i32 @pr40805(i32 %x, i32 %y, i32 %z) {
172+
%a = and i32 %x, 1
173+
%b = icmp ne i32 %a, 0
174+
%c = select i1 %b, i32 %y, i32 %z
175+
ret i32 %c
176+
}

‎llvm/test/CodeGen/WebAssembly/simd-select.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ define <16 x i8> @vselect_v16i8(<16 x i1> %c, <16 x i8> %x, <16 x i8> %y) {
2929
; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
3030
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
3131
; CHECK-NEXT: return $pop[[R]]{{$}}
32-
define <16 x i8> @select_v16i8(i1 %c, <16 x i8> %x, <16 x i8> %y) {
32+
define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %x, <16 x i8> %y) {
3333
%res = select i1 %c, <16 x i8> %x, <16 x i8> %y
3434
ret <16 x i8> %res
3535
}
@@ -99,7 +99,7 @@ define <8 x i16> @vselect_v8i16(<8 x i1> %c, <8 x i16> %x, <8 x i16> %y) {
9999
; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
100100
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
101101
; CHECK-NEXT: return $pop[[R]]{{$}}
102-
define <8 x i16> @select_v8i16(i1 %c, <8 x i16> %x, <8 x i16> %y) {
102+
define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %x, <8 x i16> %y) {
103103
%res = select i1 %c, <8 x i16> %x, <8 x i16> %y
104104
ret <8 x i16> %res
105105
}
@@ -170,7 +170,7 @@ define <4 x i32> @vselect_v4i32(<4 x i1> %c, <4 x i32> %x, <4 x i32> %y) {
170170
; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
171171
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
172172
; CHECK-NEXT: return $pop[[R]]{{$}}
173-
define <4 x i32> @select_v4i32(i1 %c, <4 x i32> %x, <4 x i32> %y) {
173+
define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %x, <4 x i32> %y) {
174174
%res = select i1 %c, <4 x i32> %x, <4 x i32> %y
175175
ret <4 x i32> %res
176176
}
@@ -240,7 +240,7 @@ define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
240240
; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
241241
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
242242
; CHECK-NEXT: return $pop[[R]]{{$}}
243-
define <2 x i64> @select_v2i64(i1 %c, <2 x i64> %x, <2 x i64> %y) {
243+
define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %x, <2 x i64> %y) {
244244
%res = select i1 %c, <2 x i64> %x, <2 x i64> %y
245245
ret <2 x i64> %res
246246
}
@@ -313,7 +313,7 @@ define <4 x float> @vselect_v4f32(<4 x i1> %c, <4 x float> %x, <4 x float> %y) {
313313
; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
314314
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
315315
; CHECK-NEXT: return $pop[[R]]{{$}}
316-
define <4 x float> @select_v4f32(i1 %c, <4 x float> %x, <4 x float> %y) {
316+
define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %x, <4 x float> %y) {
317317
%res = select i1 %c, <4 x float> %x, <4 x float> %y
318318
ret <4 x float> %res
319319
}
@@ -383,7 +383,7 @@ define <2 x double> @vselect_v2f64(<2 x i1> %c, <2 x double> %x, <2 x double> %y
383383
; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
384384
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
385385
; CHECK-NEXT: return $pop[[R]]{{$}}
386-
define <2 x double> @select_v2f64(i1 %c, <2 x double> %x, <2 x double> %y) {
386+
define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %x, <2 x double> %y) {
387387
%res = select i1 %c, <2 x double> %x, <2 x double> %y
388388
ret <2 x double> %res
389389
}

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