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Commit 4aa8bda

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espindolaespindola
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Rename features to match what gcc and clang use.
There is no advantage in being different and using the same names simplifies clang a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189141 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent f3c0314 commit 4aa8bda

13 files changed

+17
-17
lines changed

‎lib/Target/X86/X86.td

+3-3
Original file line numberDiff line numberDiff line change
@@ -50,10 +50,10 @@ def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
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def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
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def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
@@ -119,7 +119,7 @@ def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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[FeatureSSE2]>;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions">;

‎test/CodeGen/X86/bool-simplify.ll

+1-1
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@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand,+rdseed | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx,+rdrnd,+rdseed | FileCheck %s
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define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) {
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%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)

‎test/CodeGen/X86/vec_compare-sse4.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2
2-
; RUN: llc < %s -march=x86 -mattr=-sse42,+sse41 | FileCheck %s -check-prefix=SSE41
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; RUN: llc < %s -march=x86 -mattr=-sse4.2,+sse4.1 | FileCheck %s -check-prefix=SSE41
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; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
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define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {

‎test/CodeGen/X86/vec_extract.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse41 -o %t
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; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse4.1 -o %t
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; RUN: grep movss %t | count 4
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; RUN: grep movhlps %t | count 1
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; RUN: not grep pshufd %t

‎test/CodeGen/X86/vec_insert-2.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X32 %s
2-
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s
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; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | FileCheck --check-prefix=X32 %s
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; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse4.1 | FileCheck --check-prefix=X64 %s
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define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
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; X32-LABEL: t1:

‎test/CodeGen/X86/vec_insert-3.ll

+1-1
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@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep punpcklqdq | count 1
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; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse4.1 | grep punpcklqdq | count 1
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define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
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%tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1

‎test/CodeGen/X86/vec_insert.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 1
2-
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | not grep pinsrw
1+
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | grep movss | count 1
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; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | not grep pinsrw
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define void @test(<4 x float>* %F, i32 %I) nounwind {
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=1]

‎test/CodeGen/X86/vec_set.ll

+1-1
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@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep punpckl | count 7
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; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | grep punpckl | count 7
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define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
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%tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]

‎test/CodeGen/X86/vec_setcc.ll

+1-1
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@@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 | FileCheck %s -check-prefix=SSE2
2-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse41 | FileCheck %s -check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse4.1 | FileCheck %s -check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx | FileCheck %s -check-prefix=AVX
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define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {

‎test/CodeGen/X86/vec_shuffle-26.ll

+1-1
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@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -march=x86 -mcpu=generic -mattr=sse41 | FileCheck %s
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; RUN: llc < %s -march=x86 -mcpu=generic -mattr=sse4.1 | FileCheck %s
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; RUN: llc < %s -march=x86 -mcpu=atom | FileCheck -check-prefix=ATOM %s
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; Transpose example using the more generic vector shuffle. Return float8

‎test/CodeGen/X86/widen_arith-3.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s
1+
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse4.2 -post-RA-scheduler=true | FileCheck %s
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; CHECK: paddd
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; Widen a v3i16 to v8i16 to do a vector add

‎test/CodeGen/X86/widen_cast-1.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -march=x86 -mcpu=generic -mattr=+sse42 < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=generic -mattr=+sse4.2 < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
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; CHECK: paddd

‎test/CodeGen/X86/widen_load-2.ll

+1-1
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@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse42 | FileCheck %s
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; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.2 | FileCheck %s
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; Test based on pr5626 to load/store
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;

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