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arsenmarsenm
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R600/SI: Change formatting of printed FP immediates
Only 1 decimal place should be printed for inline immediates. Other constants should be hex constants. Does not include f64 tests because folding those inline immediates currently does not work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217964 91177308-0d34-0410-b5e6-96231b3b80d8
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6 files changed

+207
-24
lines changed

6 files changed

+207
-24
lines changed

‎lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp

+26-13
Original file line numberDiff line numberDiff line change
@@ -182,19 +182,27 @@ void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
182182
return;
183183
}
184184

185-
if (Imm == FloatToBits(1.0f) ||
186-
Imm == FloatToBits(-1.0f) ||
187-
Imm == FloatToBits(0.5f) ||
188-
Imm == FloatToBits(-0.5f) ||
189-
Imm == FloatToBits(2.0f) ||
190-
Imm == FloatToBits(-2.0f) ||
191-
Imm == FloatToBits(4.0f) ||
192-
Imm == FloatToBits(-4.0f)) {
193-
O << BitsToFloat(Imm);
194-
return;
185+
if (Imm == FloatToBits(0.0f))
186+
O << "0.0";
187+
else if (Imm == FloatToBits(1.0f))
188+
O << "1.0";
189+
else if (Imm == FloatToBits(-1.0f))
190+
O << "-1.0";
191+
else if (Imm == FloatToBits(0.5f))
192+
O << "0.5";
193+
else if (Imm == FloatToBits(-0.5f))
194+
O << "-0.5";
195+
else if (Imm == FloatToBits(2.0f))
196+
O << "2.0";
197+
else if (Imm == FloatToBits(-2.0f))
198+
O << "-2.0";
199+
else if (Imm == FloatToBits(4.0f))
200+
O << "4.0";
201+
else if (Imm == FloatToBits(-4.0f))
202+
O << "-4.0";
203+
else {
204+
O << formatHex(static_cast<uint64_t>(Imm));
195205
}
196-
197-
O << formatHex(static_cast<uint64_t>(Imm));
198206
}
199207

200208
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -214,7 +222,12 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
214222
} else if (Op.isImm()) {
215223
printImmediate(Op.getImm(), O);
216224
} else if (Op.isFPImm()) {
217-
O << Op.getFPImm();
225+
226+
// We special case 0.0 because otherwise it will be printed as an integer.
227+
if (Op.getFPImm() == 0.0)
228+
O << "0.0";
229+
else
230+
printImmediate(FloatToBits(Op.getFPImm()), O);
218231
} else if (Op.isExpr()) {
219232
const MCExpr *Exp = Op.getExpr();
220233
Exp->print(O);

‎test/CodeGen/R600/fneg.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %i
4848
; R600: -KC0[2].Z
4949

5050
; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
51-
; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0
51+
; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.0, s{{[0-9]}}, 0, 0
5252
define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
5353
%bc = bitcast i32 %in to float
5454
%fsub = fsub float 0.0, %bc

‎test/CodeGen/R600/imm.ll

+173-3
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
1+
; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
22

33
; Use a 64-bit value with lo bits that can be represented as an inline constant
4-
; CHECK: @i64_imm_inline_lo
4+
; CHECK-LABEL: @i64_imm_inline_lo
55
; CHECK: S_MOV_B32 [[LO:s[0-9]+]], 5
66
; CHECK: V_MOV_B32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
77
; CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_VGPR]]:
@@ -12,7 +12,7 @@ entry:
1212
}
1313

1414
; Use a 64-bit value with hi bits that can be represented as an inline constant
15-
; CHECK: @i64_imm_inline_hi
15+
; CHECK-LABEL: @i64_imm_inline_hi
1616
; CHECK: S_MOV_B32 [[HI:s[0-9]+]], 5
1717
; CHECK: V_MOV_B32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
1818
; CHECK: BUFFER_STORE_DWORDX2 v{{\[[0-9]+:}}[[HI_VGPR]]
@@ -21,3 +21,173 @@ entry:
2121
store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
2222
ret void
2323
}
24+
25+
; CHECK-LABEL: @store_inline_imm_0.0_f32
26+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0{{$}}
27+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
28+
define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
29+
store float 0.0, float addrspace(1)* %out
30+
ret void
31+
}
32+
33+
; CHECK-LABEL: @store_inline_imm_0.5_f32
34+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0.5{{$}}
35+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
36+
define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
37+
store float 0.5, float addrspace(1)* %out
38+
ret void
39+
}
40+
41+
; CHECK-LABEL: @store_inline_imm_m_0.5_f32
42+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -0.5{{$}}
43+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
44+
define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
45+
store float -0.5, float addrspace(1)* %out
46+
ret void
47+
}
48+
49+
; CHECK-LABEL: @store_inline_imm_1.0_f32
50+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0{{$}}
51+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
52+
define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
53+
store float 1.0, float addrspace(1)* %out
54+
ret void
55+
}
56+
57+
; CHECK-LABEL: @store_inline_imm_m_1.0_f32
58+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -1.0{{$}}
59+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
60+
define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
61+
store float -1.0, float addrspace(1)* %out
62+
ret void
63+
}
64+
65+
; CHECK-LABEL: @store_inline_imm_2.0_f32
66+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 2.0{{$}}
67+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
68+
define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
69+
store float 2.0, float addrspace(1)* %out
70+
ret void
71+
}
72+
73+
; CHECK-LABEL: @store_inline_imm_m_2.0_f32
74+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -2.0{{$}}
75+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
76+
define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
77+
store float -2.0, float addrspace(1)* %out
78+
ret void
79+
}
80+
81+
; CHECK-LABEL: @store_inline_imm_4.0_f32
82+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 4.0{{$}}
83+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
84+
define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
85+
store float 4.0, float addrspace(1)* %out
86+
ret void
87+
}
88+
89+
; CHECK-LABEL: @store_inline_imm_m_4.0_f32
90+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -4.0{{$}}
91+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
92+
define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
93+
store float -4.0, float addrspace(1)* %out
94+
ret void
95+
}
96+
97+
; CHECK-LABEL: @store_literal_imm_f32
98+
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x45800000
99+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
100+
define void @store_literal_imm_f32(float addrspace(1)* %out) {
101+
store float 4096.0, float addrspace(1)* %out
102+
ret void
103+
}
104+
105+
; CHECK-LABEL: @add_inline_imm_0.0_f32
106+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
107+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.0,
108+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
109+
define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
110+
%y = fadd float %x, 0.0
111+
store float %y, float addrspace(1)* %out
112+
ret void
113+
}
114+
115+
; CHECK-LABEL: @add_inline_imm_0.5_f32
116+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
117+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5,
118+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
119+
define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
120+
%y = fadd float %x, 0.5
121+
store float %y, float addrspace(1)* %out
122+
ret void
123+
}
124+
125+
; CHECK-LABEL: @add_inline_imm_neg_0.5_f32
126+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
127+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5,
128+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
129+
define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
130+
%y = fadd float %x, -0.5
131+
store float %y, float addrspace(1)* %out
132+
ret void
133+
}
134+
135+
; CHECK-LABEL: @add_inline_imm_1.0_f32
136+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
137+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0,
138+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
139+
define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
140+
%y = fadd float %x, 1.0
141+
store float %y, float addrspace(1)* %out
142+
ret void
143+
}
144+
145+
; CHECK-LABEL: @add_inline_imm_neg_1.0_f32
146+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
147+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0,
148+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
149+
define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
150+
%y = fadd float %x, -1.0
151+
store float %y, float addrspace(1)* %out
152+
ret void
153+
}
154+
155+
; CHECK-LABEL: @add_inline_imm_2.0_f32
156+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
157+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0,
158+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
159+
define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
160+
%y = fadd float %x, 2.0
161+
store float %y, float addrspace(1)* %out
162+
ret void
163+
}
164+
165+
; CHECK-LABEL: @add_inline_imm_neg_2.0_f32
166+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
167+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0,
168+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
169+
define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
170+
%y = fadd float %x, -2.0
171+
store float %y, float addrspace(1)* %out
172+
ret void
173+
}
174+
175+
; CHECK-LABEL: @add_inline_imm_4.0_f32
176+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
177+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0,
178+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
179+
define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
180+
%y = fadd float %x, 4.0
181+
store float %y, float addrspace(1)* %out
182+
ret void
183+
}
184+
185+
; CHECK-LABEL: @add_inline_imm_neg_4.0_f32
186+
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
187+
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0,
188+
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
189+
define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
190+
%y = fadd float %x, -4.0
191+
store float %y, float addrspace(1)* %out
192+
ret void
193+
}

‎test/CodeGen/R600/insert_vector_elt.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ define void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) n
4949
}
5050

5151
; SI-LABEL: @dynamic_insertelement_v2f32:
52-
; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 5.000000e+00
52+
; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 0x40a00000
5353
; SI: V_MOVRELD_B32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
5454
; SI: BUFFER_STORE_DWORDX2 {{v\[}}[[LOW_RESULT_REG]]:
5555
define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
@@ -59,7 +59,7 @@ define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x fl
5959
}
6060

6161
; SI-LABEL: @dynamic_insertelement_v4f32:
62-
; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 5.000000e+00
62+
; SI: V_MOV_B32_e32 [[CONST:v[0-9]+]], 0x40a00000
6363
; SI: V_MOVRELD_B32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
6464
; SI: BUFFER_STORE_DWORDX4 {{v\[}}[[LOW_RESULT_REG]]:
6565
define void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {

‎test/CodeGen/R600/llvm.sin.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define void @sin_f32(float addrspace(1)* %out, float %x) #1 {
2121

2222
; FUNC-LABEL: @sin_3x_f32
2323
; SI-UNSAFE-NOT: V_ADD_F32
24-
; SI-UNSAFE: 4.774648e-01
24+
; SI-UNSAFE: 0x3ef47644
2525
; SI-UNSAFE: V_MUL_F32
2626
; SI-SAFE: V_MUL_F32
2727
; SI-SAFE: V_MUL_F32
@@ -37,7 +37,7 @@ define void @sin_3x_f32(float addrspace(1)* %out, float %x) #1 {
3737

3838
; FUNC-LABEL: @sin_2x_f32
3939
; SI-UNSAFE-NOT: V_ADD_F32
40-
; SI-UNSAFE: 3.183099e-01
40+
; SI-UNSAFE: 0x3ea2f983
4141
; SI-UNSAFE: V_MUL_F32
4242
; SI-SAFE: V_ADD_F32
4343
; SI-SAFE: V_MUL_F32
@@ -52,7 +52,7 @@ define void @sin_2x_f32(float addrspace(1)* %out, float %x) #1 {
5252
}
5353

5454
; FUNC-LABEL: @test_2sin_f32
55-
; SI-UNSAFE: 3.183099e-01
55+
; SI-UNSAFE: 0x3ea2f983
5656
; SI-UNSAFE: V_MUL_F32
5757
; SI-SAFE: V_ADD_F32
5858
; SI-SAFE: V_MUL_F32

‎test/CodeGen/R600/uint_to_fp.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ entry:
4949

5050
; FUNC-LABEL: @uint_to_fp_i1_f32:
5151
; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
52-
; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.000000e+00, [[CMP]]
52+
; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
5353
; SI: BUFFER_STORE_DWORD [[RESULT]],
5454
; SI: S_ENDPGM
5555
define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) {
@@ -60,7 +60,7 @@ define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) {
6060
}
6161

6262
; FUNC-LABEL: @uint_to_fp_i1_f32_load:
63-
; SI: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.000000e+00
63+
; SI: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0
6464
; SI: BUFFER_STORE_DWORD [[RESULT]],
6565
; SI: S_ENDPGM
6666
define void @uint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 %in) {

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