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Commit 5273295

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[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.
This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero- extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both operands have to be sign-/zero-extended with separate instructions. Related to <rdar://problem/17913111>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216073 91177308-0d34-0410-b5e6-96231b3b80d8
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+31
-7
lines changed

2 files changed

+31
-7
lines changed

lib/Target/AArch64/AArch64FastISel.cpp

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -773,19 +773,27 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
773773
const Value *LHS, const Value *RHS,
774774
bool IsZExt, bool WantResult) {
775775
AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
776-
MVT SrcVT = RetVT;
776+
bool NeedExtend = false;
777777
switch (RetVT.SimpleTy) {
778-
default: return 0;
778+
default:
779+
return 0;
779780
case MVT::i1:
781+
NeedExtend = true;
782+
break;
780783
case MVT::i8:
781-
ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; RetVT = MVT::i32;
784+
NeedExtend = true;
785+
ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
782786
break;
783787
case MVT::i16:
784-
ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; RetVT = MVT::i32;
788+
NeedExtend = true;
789+
ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
790+
break;
791+
case MVT::i32: // fall-through
792+
case MVT::i64:
785793
break;
786-
case MVT::i32: break;
787-
case MVT::i64: break;
788794
}
795+
MVT SrcVT = RetVT;
796+
RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
789797

790798
// Canonicalize immediates to the RHS first.
791799
if (UseAdds && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
@@ -805,7 +813,7 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
805813
return 0;
806814
bool LHSIsKill = hasTrivialKill(LHS);
807815

808-
if (ExtendType != AArch64_AM::InvalidShiftExtend)
816+
if (NeedExtend)
809817
LHSReg = EmitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
810818

811819
unsigned ResultReg = 0;
@@ -821,6 +829,7 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
821829
if (ResultReg)
822830
return ResultReg;
823831

832+
// Only extend the RHS within the instruction if there is a valid extend type.
824833
if (ExtendType != AArch64_AM::InvalidShiftExtend) {
825834
if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
826835
if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
@@ -867,6 +876,10 @@ unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
867876
if (!RHSReg)
868877
return 0;
869878
bool RHSIsKill = hasTrivialKill(RHS);
879+
880+
if (NeedExtend)
881+
RHSReg = EmitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
882+
870883
return emitAddsSubs_rr(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
871884
WantResult);
872885
}

test/CodeGen/AArch64/arm64-fast-isel-icmp.ll

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,17 @@ entry:
172172
ret i32 %conv2
173173
}
174174

175+
define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind {
176+
entry:
177+
; CHECK-LABEL: icmp_i1_signed
178+
; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1
179+
; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1
180+
; CHECK-NEXT: cmp [[REG1]], [[REG2]]
181+
; CHECK-NEXT: cset w0, gt
182+
%cmp = icmp sgt i1 %a, %b
183+
%conv2 = zext i1 %cmp to i32
184+
ret i32 %conv2
185+
}
175186

176187
define i32 @icmp_i16_signed_const(i16 %a) nounwind {
177188
entry:

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