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TMP: work around PR33883
Include the proposed patch at https://reviews.llvm.org/D35765
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lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+24-15
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,27 @@ LimitFPPrecision("limit-float-precision",
9999
// store [4096 x i8] %data, [4096 x i8]* %buffer
100100
static const unsigned MaxParallelChains = 64;
101101

102+
// True if the Value passed requires ABI mangling as it is a parameter to a
103+
// function or a return value from a function which is not an intrinsic.
104+
static bool isABIRegCopy(const Value * V) {
105+
const bool IsRetInst = V && isa<ReturnInst>(V);
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const bool IsCallInst = V && isa<CallInst>(V);
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const bool IsInLineAsm =
108+
IsCallInst && static_cast<const CallInst *>(V)->isInlineAsm();
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const bool IsIndirectFunctionCall =
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IsCallInst && !IsInLineAsm &&
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!static_cast<const CallInst *>(V)->getCalledFunction();
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// It is possible that the call instruction is an inline asm statement or an
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// indirect function call in which case the return value of
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// getCalledFunction() would be nullptr.
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const bool IsInstrinsicCall =
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IsCallInst && !IsInLineAsm && !IsIndirectFunctionCall &&
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static_cast<const CallInst *>(V)->getCalledFunction()->getIntrinsicID() !=
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Intrinsic::not_intrinsic;
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return IsRetInst || (IsCallInst && (!IsInLineAsm && !IsInstrinsicCall));
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}
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102123
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
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const SDValue *Parts, unsigned NumParts,
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MVT PartVT, EVT ValueVT, const Value *V,
@@ -1026,13 +1047,9 @@ SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
10261047

10271048
if (It != FuncInfo.ValueMap.end()) {
10281049
unsigned InReg = It->second;
1029-
bool IsABIRegCopy =
1030-
V && ((isa<CallInst>(V) &&
1031-
!(static_cast<const CallInst *>(V))->isInlineAsm()) ||
1032-
isa<ReturnInst>(V));
10331050

10341051
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1035-
DAG.getDataLayout(), InReg, Ty, IsABIRegCopy);
1052+
DAG.getDataLayout(), InReg, Ty, isABIRegCopy(V));
10361053
SDValue Chain = DAG.getEntryNode();
10371054
Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
10381055
V);
@@ -1221,13 +1238,9 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
12211238
// If this is an instruction which fast-isel has deferred, select it now.
12221239
if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
12231240
unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1224-
bool IsABIRegCopy =
1225-
V && ((isa<CallInst>(V) &&
1226-
!(static_cast<const CallInst *>(V))->isInlineAsm()) ||
1227-
isa<ReturnInst>(V));
12281241

12291242
RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1230-
Inst->getType(), IsABIRegCopy);
1243+
Inst->getType(), isABIRegCopy(V));
12311244
SDValue Chain = DAG.getEntryNode();
12321245
return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
12331246
}
@@ -8281,13 +8294,9 @@ SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
82818294
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
82828295
// If this is an InlineAsm we have to match the registers required, not the
82838296
// notional registers required by the type.
8284-
bool IsABIRegCopy =
8285-
V && ((isa<CallInst>(V) &&
8286-
!(static_cast<const CallInst *>(V))->isInlineAsm()) ||
8287-
isa<ReturnInst>(V));
82888297

82898298
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
8290-
V->getType(), IsABIRegCopy);
8299+
V->getType(), isABIRegCopy(V));
82918300
SDValue Chain = DAG.getEntryNode();
82928301

82938302
ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==

test/CodeGen/Mips/cconv/pr33883.ll

+12
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
; RUN: llc -march=mips -mcpu=mips32 < %s -o /dev/null
2+
3+
; Test that calls to vector intrinsics do not crash SelectionDAGBuilder.
4+
5+
define <4 x float> @_ZN4simd3foo17hebb969c5fb39a194E(<4 x float>) {
6+
start:
7+
%1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
8+
9+
ret <4 x float> %1
10+
}
11+
12+
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)

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