Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit 9028826

Browse files
committed
[MSP430] Fix PR32769: Select8 and Select16 need to have SR in Uses.
If Select pseudo instruction doesn't have use SR, then CMP instructions are being marked as dead and later can be removed by MachineCSE pass. This leads to incorrect code generation. Differential Revision: https://reviews.llvm.org/D32473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301372 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 878af19 commit 9028826

File tree

2 files changed

+23
-0
lines changed

2 files changed

+23
-0
lines changed

lib/Target/MSP430/MSP430InstrInfo.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
122122
}
123123

124124
let usesCustomInserter = 1 in {
125+
let Uses = [SR] in {
125126
def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
126127
"# Select8 PSEUDO",
127128
[(set GR8:$dst,
@@ -130,6 +131,7 @@ let usesCustomInserter = 1 in {
130131
"# Select16 PSEUDO",
131132
[(set GR16:$dst,
132133
(MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
134+
}
133135
let Defs = [SR] in {
134136
def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
135137
"# Shl8 PSEUDO",

test/CodeGen/MSP430/select-use-sr.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; RUN: llc < %s -march=msp430 | FileCheck %s
2+
; PR32769
3+
4+
target triple = "msp430"
5+
6+
; Test that CMP instruction is not removed by MachineCSE.
7+
;
8+
; CHECK-LABEL: @f
9+
; CHECK: cmp.w r15, r13
10+
; CHECK: cmp.w r15, r13
11+
; CHECK-NEXT: jeq .LBB0_2
12+
define i16 @f(i16, i16, i16, i16) {
13+
entry:
14+
%4 = icmp ult i16 %1, %3
15+
%5 = zext i1 %4 to i16
16+
%6 = icmp ult i16 %0, %2
17+
%7 = zext i1 %6 to i16
18+
%8 = icmp eq i16 %1, %3
19+
%out = select i1 %8, i16 %5, i16 %7
20+
ret i16 %out
21+
}

0 commit comments

Comments
 (0)