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alexcrichtonalexcrichton
authored
Merge pull request #113 from cuviper/merge-release_60
Merge upstream branch `release_60`
2 parents efe8743 + 2de9cac commit fd7dd99

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57 files changed

+2985
-107
lines changed

‎CMakeLists.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
2424
set(LLVM_VERSION_MINOR 0)
2525
endif()
2626
if(NOT DEFINED LLVM_VERSION_PATCH)
27-
set(LLVM_VERSION_PATCH 0)
27+
set(LLVM_VERSION_PATCH 1)
2828
endif()
2929
if(NOT DEFINED LLVM_VERSION_SUFFIX)
3030
set(LLVM_VERSION_SUFFIX "")

‎include/llvm/CodeGen/TargetInstrInfo.h

+6-3
Original file line numberDiff line numberDiff line change
@@ -421,7 +421,8 @@ class TargetInstrInfo : public MCInstrInfo {
421421
/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
422422
/// and \p DefIdx.
423423
/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
424-
/// the list is modeled as <Reg:SubReg, SubIdx>.
424+
/// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
425+
/// flag are not added to this list.
425426
/// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
426427
/// two elements:
427428
/// - %1:sub1, sub0
@@ -446,7 +447,8 @@ class TargetInstrInfo : public MCInstrInfo {
446447
/// - %1:sub1, sub0
447448
///
448449
/// \returns true if it is possible to build such an input sequence
449-
/// with the pair \p MI, \p DefIdx. False otherwise.
450+
/// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
451+
/// False otherwise.
450452
///
451453
/// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
452454
///
@@ -465,7 +467,8 @@ class TargetInstrInfo : public MCInstrInfo {
465467
/// - InsertedReg: %1:sub1, sub3
466468
///
467469
/// \returns true if it is possible to build such an input sequence
468-
/// with the pair \p MI, \p DefIdx. False otherwise.
470+
/// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
471+
/// False otherwise.
469472
///
470473
/// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
471474
///

‎lib/Analysis/GlobalsModRef.cpp

+2
Original file line numberDiff line numberDiff line change
@@ -502,6 +502,8 @@ void GlobalsAAResult::AnalyzeCallGraph(CallGraph &CG, Module &M) {
502502
}
503503

504504
FunctionInfo &FI = FunctionInfos[F];
505+
Handles.emplace_front(*this, F);
506+
Handles.front().I = Handles.begin();
505507
bool KnowNothing = false;
506508

507509
// Collect the mod/ref properties due to called functions. We only compute

‎lib/Analysis/MemorySSA.cpp

+20-9
Original file line numberDiff line numberDiff line change
@@ -153,9 +153,14 @@ class MemoryLocOrCall {
153153
if (IsCall != Other.IsCall)
154154
return false;
155155

156-
if (IsCall)
157-
return CS.getCalledValue() == Other.CS.getCalledValue();
158-
return Loc == Other.Loc;
156+
if (!IsCall)
157+
return Loc == Other.Loc;
158+
159+
if (CS.getCalledValue() != Other.CS.getCalledValue())
160+
return false;
161+
162+
return CS.arg_size() == Other.CS.arg_size() &&
163+
std::equal(CS.arg_begin(), CS.arg_end(), Other.CS.arg_begin());
159164
}
160165

161166
private:
@@ -179,12 +184,18 @@ template <> struct DenseMapInfo<MemoryLocOrCall> {
179184
}
180185

181186
static unsigned getHashValue(const MemoryLocOrCall &MLOC) {
182-
if (MLOC.IsCall)
183-
return hash_combine(MLOC.IsCall,
184-
DenseMapInfo<const Value *>::getHashValue(
185-
MLOC.getCS().getCalledValue()));
186-
return hash_combine(
187-
MLOC.IsCall, DenseMapInfo<MemoryLocation>::getHashValue(MLOC.getLoc()));
187+
if (!MLOC.IsCall)
188+
return hash_combine(
189+
MLOC.IsCall,
190+
DenseMapInfo<MemoryLocation>::getHashValue(MLOC.getLoc()));
191+
192+
hash_code hash =
193+
hash_combine(MLOC.IsCall, DenseMapInfo<const Value *>::getHashValue(
194+
MLOC.getCS().getCalledValue()));
195+
196+
for (const Value *Arg : MLOC.getCS().args())
197+
hash = hash_combine(hash, DenseMapInfo<const Value *>::getHashValue(Arg));
198+
return hash;
188199
}
189200

190201
static bool isEqual(const MemoryLocOrCall &LHS, const MemoryLocOrCall &RHS) {

‎lib/CodeGen/LiveDebugVariables.cpp

+5-2
Original file line numberDiff line numberDiff line change
@@ -557,8 +557,11 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
557557
getUserValue(Var, Expr, MI.getDebugLoc());
558558
if (!Discard)
559559
UV->addDef(Idx, MI.getOperand(0), IsIndirect);
560-
else
561-
UV->addDef(Idx, MachineOperand::CreateReg(0U, RegState::Debug), false);
560+
else {
561+
MachineOperand MO = MachineOperand::CreateReg(0U, false);
562+
MO.setIsDebug();
563+
UV->addDef(Idx, MO, false);
564+
}
562565
return true;
563566
}
564567

‎lib/CodeGen/PeepholeOptimizer.cpp

+16-3
Original file line numberDiff line numberDiff line change
@@ -1882,6 +1882,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
18821882
return ValueTrackerResult();
18831883
// Otherwise, we want the whole source.
18841884
const MachineOperand &Src = Def->getOperand(1);
1885+
if (Src.isUndef())
1886+
return ValueTrackerResult();
18851887
return ValueTrackerResult(Src.getReg(), Src.getSubReg());
18861888
}
18871889

@@ -1925,6 +1927,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
19251927
}
19261928

19271929
const MachineOperand &Src = Def->getOperand(SrcIdx);
1930+
if (Src.isUndef())
1931+
return ValueTrackerResult();
19281932
return ValueTrackerResult(Src.getReg(), Src.getSubReg());
19291933
}
19301934

@@ -2093,6 +2097,10 @@ ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
20932097
for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
20942098
auto &MO = Def->getOperand(i);
20952099
assert(MO.isReg() && "Invalid PHI instruction");
2100+
// We have no code to deal with undef operands. They shouldn't happen in
2101+
// normal programs anyway.
2102+
if (MO.isUndef())
2103+
return ValueTrackerResult();
20962104
Res.addSource(MO.getReg(), MO.getSubReg());
20972105
}
20982106

@@ -2149,9 +2157,14 @@ ValueTrackerResult ValueTracker::getNextSource() {
21492157
// If we can still move up in the use-def chain, move to the next
21502158
// definition.
21512159
if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
2152-
Def = MRI.getVRegDef(Reg);
2153-
DefIdx = MRI.def_begin(Reg).getOperandNo();
2154-
DefSubReg = Res.getSrcSubReg(0);
2160+
MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
2161+
if (DI != MRI.def_end()) {
2162+
Def = DI->getParent();
2163+
DefIdx = DI.getOperandNo();
2164+
DefSubReg = Res.getSrcSubReg(0);
2165+
} else {
2166+
Def = nullptr;
2167+
}
21552168
return Res;
21562169
}
21572170
}

‎lib/CodeGen/TargetInstrInfo.cpp

+6
Original file line numberDiff line numberDiff line change
@@ -1151,6 +1151,8 @@ bool TargetInstrInfo::getRegSequenceInputs(
11511151
for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
11521152
OpIdx += 2) {
11531153
const MachineOperand &MOReg = MI.getOperand(OpIdx);
1154+
if (MOReg.isUndef())
1155+
continue;
11541156
const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
11551157
assert(MOSubIdx.isImm() &&
11561158
"One of the subindex of the reg_sequence is not an immediate");
@@ -1174,6 +1176,8 @@ bool TargetInstrInfo::getExtractSubregInputs(
11741176
// Def = EXTRACT_SUBREG v0.sub1, sub0.
11751177
assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
11761178
const MachineOperand &MOReg = MI.getOperand(1);
1179+
if (MOReg.isUndef())
1180+
return false;
11771181
const MachineOperand &MOSubIdx = MI.getOperand(2);
11781182
assert(MOSubIdx.isImm() &&
11791183
"The subindex of the extract_subreg is not an immediate");
@@ -1198,6 +1202,8 @@ bool TargetInstrInfo::getInsertSubregInputs(
11981202
assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
11991203
const MachineOperand &MOBaseReg = MI.getOperand(1);
12001204
const MachineOperand &MOInsertedReg = MI.getOperand(2);
1205+
if (MOInsertedReg.isUndef())
1206+
return false;
12011207
const MachineOperand &MOSubIdx = MI.getOperand(3);
12021208
assert(MOSubIdx.isImm() &&
12031209
"One of the subindex of the reg_sequence is not an immediate");

‎lib/Support/Host.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1009,7 +1009,7 @@ StringRef sys::getHostCPUName() {
10091009
#include "llvm/Support/X86TargetParser.def"
10101010

10111011
// Now check types.
1012-
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1012+
#define X86_CPU_TYPE(ARCHNAME, ENUM) \
10131013
if (Type == X86::ENUM) \
10141014
return ARCHNAME;
10151015
#include "llvm/Support/X86TargetParser.def"

‎lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

+18
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@
4646
#include "llvm/Pass.h"
4747
#include "llvm/Support/Casting.h"
4848
#include "llvm/Support/Debug.h"
49+
#include "llvm/Support/DebugCounter.h"
4950
#include "llvm/Support/raw_ostream.h"
5051
#include <cassert>
5152
#include <iterator>
@@ -60,6 +61,8 @@ STATISTIC(NumCollisionsAvoided,
6061
"Number of HW prefetch tag collisions avoided");
6162
STATISTIC(NumCollisionsNotAvoided,
6263
"Number of HW prefetch tag collisions not avoided due to lack of regsiters");
64+
DEBUG_COUNTER(FixCounter, "falkor-hwpf",
65+
"Controls which tag collisions are avoided");
6366

6467
namespace {
6568

@@ -729,6 +732,21 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
729732
bool Fixed = false;
730733
DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);
731734

735+
if (!DebugCounter::shouldExecute(FixCounter)) {
736+
DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI);
737+
continue;
738+
}
739+
740+
// Add the non-base registers of MI as live so we don't use them as
741+
// scratch registers.
742+
for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) {
743+
if (OpI == static_cast<unsigned>(LdI.BaseRegIdx))
744+
continue;
745+
MachineOperand &MO = MI.getOperand(OpI);
746+
if (MO.isReg() && MO.readsReg())
747+
LR.addReg(MO.getReg());
748+
}
749+
732750
for (unsigned ScratchReg : AArch64::GPR64RegClass) {
733751
if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
734752
continue;

‎lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
147147
initializeR600PacketizerPass(*PR);
148148
initializeR600ExpandSpecialInstrsPassPass(*PR);
149149
initializeR600VectorRegMergerPass(*PR);
150+
initializeGlobalISel(*PR);
150151
initializeAMDGPUDAGToDAGISelPass(*PR);
151152
initializeSILowerI1CopiesPass(*PR);
152153
initializeSIFixSGPRCopiesPass(*PR);

‎lib/Target/AMDGPU/SIISelLowering.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -358,6 +358,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
358358
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
359359
setOperationAction(ISD::CTLZ, MVT::i16, Promote);
360360
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
361+
setOperationAction(ISD::CTPOP, MVT::i16, Promote);
361362

362363
setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
363364

‎lib/Target/AMDGPU/SIInstructions.td

+4
Original file line numberDiff line numberDiff line change
@@ -726,6 +726,10 @@ def : GCNPat <
726726
(i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
727727
(V_BCNT_U32_B32_e64 $popcnt, $val)
728728
>;
729+
def : GCNPat <
730+
(i16 (add (i16 (trunc (ctpop i32:$popcnt))), i16:$val)),
731+
(V_BCNT_U32_B32_e64 $popcnt, $val)
732+
>;
729733

730734
/********** ============================================ **********/
731735
/********** Extraction, Insertion, Building and Casting **********/

‎lib/Target/ARM/ARMBaseInstrInfo.cpp

+10-4
Original file line numberDiff line numberDiff line change
@@ -4864,12 +4864,14 @@ bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
48644864
// Populate the InputRegs accordingly.
48654865
// rY
48664866
const MachineOperand *MOReg = &MI.getOperand(1);
4867-
InputRegs.push_back(
4868-
RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4867+
if (!MOReg->isUndef())
4868+
InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
4869+
MOReg->getSubReg(), ARM::ssub_0));
48694870
// rZ
48704871
MOReg = &MI.getOperand(2);
4871-
InputRegs.push_back(
4872-
RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4872+
if (!MOReg->isUndef())
4873+
InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
4874+
MOReg->getSubReg(), ARM::ssub_1));
48734875
return true;
48744876
}
48754877
llvm_unreachable("Target dependent opcode missing");
@@ -4888,6 +4890,8 @@ bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
48884890
// rX = EXTRACT_SUBREG dZ, ssub_0
48894891
// rY = EXTRACT_SUBREG dZ, ssub_1
48904892
const MachineOperand &MOReg = MI.getOperand(2);
4893+
if (MOReg.isUndef())
4894+
return false;
48914895
InputReg.Reg = MOReg.getReg();
48924896
InputReg.SubReg = MOReg.getSubReg();
48934897
InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
@@ -4907,6 +4911,8 @@ bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
49074911
// dX = VSETLNi32 dY, rZ, imm
49084912
const MachineOperand &MOBaseReg = MI.getOperand(1);
49094913
const MachineOperand &MOInsertedReg = MI.getOperand(2);
4914+
if (MOInsertedReg.isUndef())
4915+
return false;
49104916
const MachineOperand &MOIndex = MI.getOperand(3);
49114917
BaseReg.Reg = MOBaseReg.getReg();
49124918
BaseReg.SubReg = MOBaseReg.getSubReg();

‎lib/Target/ARM/ARMComputeBlockSize.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ mayOptimizeThumb2Instruction(const MachineInstr *MI) {
3535
case ARM::tBcc:
3636
// optimizeThumb2JumpTables.
3737
case ARM::t2BR_JT:
38+
case ARM::tBR_JTr:
3839
return true;
3940
}
4041
return false;

‎lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
51365136
// It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
51375137
// and registers Rd and Base for microMIPS lwp instruction
51385138
case Mips::JALR_HB:
5139+
case Mips::JALR_HB64:
51395140
case Mips::JALRC_HB_MMR6:
51405141
case Mips::JALRC_MMR6:
51415142
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())

‎lib/Target/Mips/MicroMips32r6InstrInfo.td

+6
Original file line numberDiff line numberDiff line change
@@ -1886,6 +1886,12 @@ let AddedComplexity = 41 in {
18861886

18871887
def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
18881888

1889+
def TAILCALLREG_MMR6 : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1890+
1891+
def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1892+
GPR32Opnd>,
1893+
ISA_MICROMIPS32R6;
1894+
18891895
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
18901896
(TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
18911897

‎lib/Target/Mips/MicroMipsInstrInfo.td

+6
Original file line numberDiff line numberDiff line change
@@ -1003,6 +1003,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
10031003

10041004
def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6;
10051005

1006+
def TAILCALLREG_MM : TailCallReg<JRC16_MM, GPR32Opnd>,
1007+
ISA_MICROMIPS32_NOT_MIPS32R6;
1008+
1009+
def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,
1010+
ISA_MICROMIPS32_NOT_MIPS32R6;
1011+
10061012
let DecoderNamespace = "MicroMips" in {
10071013
def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
10081014
RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;

‎lib/Target/Mips/Mips.td

+4
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,10 @@ def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
193193
def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
194194
"Disable use of the jal instruction">;
195195

196+
def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
197+
"UseIndirectJumpsHazard",
198+
"true", "Use indirect jump"
199+
" guards to prevent certain speculation based attacks">;
196200
//===----------------------------------------------------------------------===//
197201
// Mips processors supported.
198202
//===----------------------------------------------------------------------===//

‎lib/Target/Mips/Mips32r6InstrInfo.td

+39
Original file line numberDiff line numberDiff line change
@@ -1036,3 +1036,42 @@ def : MipsPat<(select i32:$cond, immz, i32:$f),
10361036
(SELEQZ i32:$f, i32:$cond)>,
10371037
ISA_MIPS32R6;
10381038
}
1039+
1040+
// Pseudo instructions
1041+
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
1042+
hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
1043+
class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
1044+
PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1045+
PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
1046+
}
1047+
1048+
class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,
1049+
RegisterOperand RO> :
1050+
MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1051+
II_IndirectBranchPseudo>,
1052+
PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {
1053+
let isTerminator=1;
1054+
let isBarrier=1;
1055+
let hasDelaySlot = 1;
1056+
let isBranch = 1;
1057+
let isIndirectBranch = 1;
1058+
bit isCTI = 1;
1059+
}
1060+
1061+
1062+
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1063+
NoIndirectJumpGuards] in {
1064+
def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;
1065+
def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,
1066+
GPR32Opnd>,
1067+
ISA_MIPS32R6;
1068+
}
1069+
1070+
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1071+
UseIndirectJumpsHazard] in {
1072+
def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6;
1073+
def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6,
1074+
GPR32Opnd>,
1075+
ISA_MIPS32R6;
1076+
}
1077+

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