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[AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructions.
Increment/decrement vector by multiple of predicate constraint element count. The variants added by this patch are: - INCH, INCW, INC and (saturating): - SQINCH, SQINCW, SQINCD - UQINCH, UQINCW, UQINCW - SQDECH, SQINCW, SQINCD - UQDECH, UQINCW, UQINCW For example: incw z0.s, all, mul #4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336090 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64SVEInstrInfo.td

+19
Original file line numberDiff line numberDiff line change
@@ -574,6 +574,25 @@ let Predicates = [HasSVE] in {
574574
defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
575575
defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
576576

577+
defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>;
578+
defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>;
579+
defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>;
580+
defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>;
581+
defm INCH_ZPiI : sve_int_countvlv<0b01100, "inch", ZPR16>;
582+
defm DECH_ZPiI : sve_int_countvlv<0b01101, "dech", ZPR16>;
583+
defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>;
584+
defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>;
585+
defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>;
586+
defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>;
587+
defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>;
588+
defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>;
589+
defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>;
590+
defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>;
591+
defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>;
592+
defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>;
593+
defm INCD_ZPiI : sve_int_countvlv<0b11100, "incd", ZPR64>;
594+
defm DECD_ZPiI : sve_int_countvlv<0b11101, "decd", ZPR64>;
595+
577596
defm INDEX_RR : sve_int_index_rr<"index">;
578597
defm INDEX_IR : sve_int_index_ir<"index">;
579598
defm INDEX_RI : sve_int_index_ri<"index">;

‎lib/Target/AArch64/SVEInstrFormats.td

+30
Original file line numberDiff line numberDiff line change
@@ -285,6 +285,36 @@ let Predicates = [HasSVE] in {
285285
// SVE Element Count Group
286286
//===----------------------------------------------------------------------===//
287287

288+
class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
289+
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
290+
asm, "\t$Zdn, $pattern, mul $imm4",
291+
"",
292+
[]>, Sched<[]> {
293+
bits<5> Zdn;
294+
bits<5> pattern;
295+
bits<4> imm4;
296+
let Inst{31-24} = 0b00000100;
297+
let Inst{23-22} = opc{4-3};
298+
let Inst{21} = 0b1;
299+
let Inst{20} = opc{2};
300+
let Inst{19-16} = imm4;
301+
let Inst{15-12} = 0b1100;
302+
let Inst{11-10} = opc{1-0};
303+
let Inst{9-5} = pattern;
304+
let Inst{4-0} = Zdn;
305+
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let Constraints = "$Zdn = $_Zdn";
307+
}
308+
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multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> {
310+
def NAME : sve_int_countvlv<opc, asm, zprty>;
311+
312+
def : InstAlias<asm # "\t$Zdn, $pattern",
313+
(!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
314+
def : InstAlias<asm # "\t$Zdn",
315+
(!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>;
316+
}
317+
288318
class sve_int_pred_pattern_a<bits<3> opc, string asm>
289319
: I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
290320
asm, "\t$Rdn, $pattern, mul $imm4",

‎test/MC/AArch64/SVE/incb-diagnostics.s

+6
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,12 @@ incb sp
1313
// CHECK-NEXT: incb sp
1414
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1515

16+
// INCB does not have a vector equivalent
17+
incb z0.b
18+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
19+
// CHECK-NEXT: incb z0.b
20+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21+
1622

1723
// ------------------------------------------------------------------------- //
1824
// Immediate not compatible with encode/decode function.

‎test/MC/AArch64/SVE/incd-diagnostics.s

+6
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,12 @@ incd sp
1313
// CHECK-NEXT: incd sp
1414
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1515

16+
// incd requires z0.d
17+
incd z0.s
18+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
19+
// CHECK-NEXT: incd z0.s
20+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21+
1622

1723
// ------------------------------------------------------------------------- //
1824
// Immediate not compatible with encode/decode function.

‎test/MC/AArch64/SVE/incd.s

+38
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,39 @@
77
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
88
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
99

10+
// ---------------------------------------------------------------------------//
11+
// Test vector form and aliases.
12+
// ---------------------------------------------------------------------------//
13+
14+
incd z0.d
15+
// CHECK-INST: incd z0.d
16+
// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
17+
// CHECK-ERROR: instruction requires: sve
18+
// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
19+
20+
incd z0.d, all
21+
// CHECK-INST: incd z0.d
22+
// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
23+
// CHECK-ERROR: instruction requires: sve
24+
// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
25+
26+
incd z0.d, all, mul #1
27+
// CHECK-INST: incd z0.d
28+
// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
29+
// CHECK-ERROR: instruction requires: sve
30+
// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
31+
32+
incd z0.d, all, mul #16
33+
// CHECK-INST: incd z0.d, all, mul #16
34+
// CHECK-ENCODING: [0xe0,0xc3,0xff,0x04]
35+
// CHECK-ERROR: instruction requires: sve
36+
// CHECK-UNKNOWN: e0 c3 ff 04 <unknown>
37+
38+
39+
// ---------------------------------------------------------------------------//
40+
// Test scalar form and aliases.
41+
// ---------------------------------------------------------------------------//
42+
1043
incd x0
1144
// CHECK-INST: incd x0
1245
// CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
@@ -31,6 +64,11 @@ incd x0, all, mul #16
3164
// CHECK-ERROR: instruction requires: sve
3265
// CHECK-UNKNOWN: e0 e3 ff 04 <unknown>
3366

67+
68+
// ---------------------------------------------------------------------------//
69+
// Test predicate patterns
70+
// ---------------------------------------------------------------------------//
71+
3472
incd x0, pow2
3573
// CHECK-INST: incd x0, pow2
3674
// CHECK-ENCODING: [0x00,0xe0,0xf0,0x04]

‎test/MC/AArch64/SVE/inch-diagnostics.s

+6
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,12 @@ inch sp
1313
// CHECK-NEXT: inch sp
1414
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1515

16+
// inch requires z0.h
17+
inch z0.s
18+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
19+
// CHECK-NEXT: inch z0.s
20+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21+
1622

1723
// ------------------------------------------------------------------------- //
1824
// Immediate not compatible with encode/decode function.

‎test/MC/AArch64/SVE/inch.s

+38
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,39 @@
77
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
88
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
99

10+
// ---------------------------------------------------------------------------//
11+
// Test vector form and aliases.
12+
// ---------------------------------------------------------------------------//
13+
14+
inch z0.h
15+
// CHECK-INST: inch z0.h
16+
// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
17+
// CHECK-ERROR: instruction requires: sve
18+
// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
19+
20+
inch z0.h, all
21+
// CHECK-INST: inch z0.h
22+
// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
23+
// CHECK-ERROR: instruction requires: sve
24+
// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
25+
26+
inch z0.h, all, mul #1
27+
// CHECK-INST: inch z0.h
28+
// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
29+
// CHECK-ERROR: instruction requires: sve
30+
// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
31+
32+
inch z0.h, all, mul #16
33+
// CHECK-INST: inch z0.h, all, mul #16
34+
// CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04]
35+
// CHECK-ERROR: instruction requires: sve
36+
// CHECK-UNKNOWN: e0 c3 7f 04 <unknown>
37+
38+
39+
// ---------------------------------------------------------------------------//
40+
// Test scalar form and aliases.
41+
// ---------------------------------------------------------------------------//
42+
1043
inch x0
1144
// CHECK-INST: inch x0
1245
// CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
@@ -31,6 +64,11 @@ inch x0, all, mul #16
3164
// CHECK-ERROR: instruction requires: sve
3265
// CHECK-UNKNOWN: e0 e3 7f 04 <unknown>
3366

67+
68+
// ---------------------------------------------------------------------------//
69+
// Test predicate patterns
70+
// ---------------------------------------------------------------------------//
71+
3472
inch x0, pow2
3573
// CHECK-INST: inch x0, pow2
3674
// CHECK-ENCODING: [0x00,0xe0,0x70,0x04]

‎test/MC/AArch64/SVE/incw-diagnostics.s

+6
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,12 @@ incw sp
1313
// CHECK-NEXT: incw sp
1414
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1515

16+
// incw requires z0.s
17+
incw z0.d
18+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
19+
// CHECK-NEXT: incw z0.d
20+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21+
1622

1723
// ------------------------------------------------------------------------- //
1824
// Immediate not compatible with encode/decode function.

‎test/MC/AArch64/SVE/incw.s

+39
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,39 @@
77
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
88
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
99

10+
// ---------------------------------------------------------------------------//
11+
// Test vector form and aliases.
12+
// ---------------------------------------------------------------------------//
13+
14+
incw z0.s
15+
// CHECK-INST: incw z0.s
16+
// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
17+
// CHECK-ERROR: instruction requires: sve
18+
// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
19+
20+
incw z0.s, all
21+
// CHECK-INST: incw z0.s
22+
// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
23+
// CHECK-ERROR: instruction requires: sve
24+
// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
25+
26+
incw z0.s, all, mul #1
27+
// CHECK-INST: incw z0.s
28+
// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
29+
// CHECK-ERROR: instruction requires: sve
30+
// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
31+
32+
incw z0.s, all, mul #16
33+
// CHECK-INST: incw z0.s, all, mul #16
34+
// CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04]
35+
// CHECK-ERROR: instruction requires: sve
36+
// CHECK-UNKNOWN: e0 c3 bf 04 <unknown>
37+
38+
39+
// ---------------------------------------------------------------------------//
40+
// Test scalar form and aliases.
41+
// ---------------------------------------------------------------------------//
42+
1043
incw x0
1144
// CHECK-INST: incw x0
1245
// CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
@@ -31,6 +64,12 @@ incw x0, all, mul #16
3164
// CHECK-ERROR: instruction requires: sve
3265
// CHECK-UNKNOWN: e0 e3 bf 04 <unknown>
3366

67+
68+
// ---------------------------------------------------------------------------//
69+
// Test predicate patterns
70+
// ---------------------------------------------------------------------------//
71+
72+
3473
incw x0, pow2
3574
// CHECK-INST: incw x0, pow2
3675
// CHECK-ENCODING: [0x00,0xe0,0xb0,0x04]

‎test/MC/AArch64/SVE/sqdecb-diagnostics.s

+5
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,11 @@ sqdecb sp
1818
// CHECK-NEXT: sqdecb sp
1919
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2020

21+
sqdecb z0.b
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
23+
// CHECK-NEXT: sqdecb z0.b
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
2126

2227
// ------------------------------------------------------------------------- //
2328
// Operands not matching up

‎test/MC/AArch64/SVE/sqdecd-diagnostics.s

+5
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,11 @@ sqdecd sp
1818
// CHECK-NEXT: sqdecd sp
1919
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2020

21+
uqdecd z0.s
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: uqdecd z0.s
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
2126

2227
// ------------------------------------------------------------------------- //
2328
// Operands not matching up

‎test/MC/AArch64/SVE/sqdecd.s

+40
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,46 @@ sqdecd x0, w0, pow2, mul #16
7777
// CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
7878

7979

80+
// ---------------------------------------------------------------------------//
81+
// Test vector form and aliases.
82+
// ---------------------------------------------------------------------------//
83+
sqdecd z0.d
84+
// CHECK-INST: sqdecd z0.d
85+
// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
86+
// CHECK-ERROR: instruction requires: sve
87+
// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
88+
89+
sqdecd z0.d, all
90+
// CHECK-INST: sqdecd z0.d
91+
// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
92+
// CHECK-ERROR: instruction requires: sve
93+
// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
94+
95+
sqdecd z0.d, all, mul #1
96+
// CHECK-INST: sqdecd z0.d
97+
// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
98+
// CHECK-ERROR: instruction requires: sve
99+
// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
100+
101+
sqdecd z0.d, all, mul #16
102+
// CHECK-INST: sqdecd z0.d, all, mul #16
103+
// CHECK-ENCODING: [0xe0,0xcb,0xef,0x04]
104+
// CHECK-ERROR: instruction requires: sve
105+
// CHECK-UNKNOWN: e0 cb ef 04 <unknown>
106+
107+
sqdecd z0.d, pow2
108+
// CHECK-INST: sqdecd z0.d, pow2
109+
// CHECK-ENCODING: [0x00,0xc8,0xe0,0x04]
110+
// CHECK-ERROR: instruction requires: sve
111+
// CHECK-UNKNOWN: 00 c8 e0 04 <unknown>
112+
113+
sqdecd z0.d, pow2, mul #16
114+
// CHECK-INST: sqdecd z0.d, pow2, mul #16
115+
// CHECK-ENCODING: [0x00,0xc8,0xef,0x04]
116+
// CHECK-ERROR: instruction requires: sve
117+
// CHECK-UNKNOWN: 00 c8 ef 04 <unknown>
118+
119+
80120
// ---------------------------------------------------------------------------//
81121
// Test all patterns for 64-bit form
82122
// ---------------------------------------------------------------------------//

‎test/MC/AArch64/SVE/sqdech-diagnostics.s

+5
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,11 @@ sqdech sp
1818
// CHECK-NEXT: sqdech sp
1919
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2020

21+
sqdech z0.s
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: sqdech z0.s
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
2126

2227
// ------------------------------------------------------------------------- //
2328
// Operands not matching up

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