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Auto merge of #43711 - lu-zero:master, r=nagisa
More Altivec intrinsics Beside the usual json + generated files, I added two additional modifiers in the generator.
2 parents ddc02de + 8b78ea5 commit 215e0b1

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3 files changed

+198
-1
lines changed

3 files changed

+198
-1
lines changed

‎src/etc/platform-intrinsics/generator.py

+9-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
SPEC = re.compile(
2020
r'^(?:(?P<void>V)|(?P<id>[iusfIUSF])(?:\((?P<start>\d+)-(?P<end>\d+)\)|'
2121
r'(?P<width>\d+)(:?/(?P<llvm_width>\d+))?)'
22-
r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMC]*)(?P<force_width>x\d+)?'
22+
r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMCNW]*)(?P<force_width>x\d+)?'
2323
r'(?:(?P<pointer>Pm|Pc)(?P<llvm_pointer>/.*)?|(?P<bitcast>->.*))?$'
2424
)
2525

@@ -246,6 +246,12 @@ def modify(self, spec, width, previous):
246246
return Vector(self._elem, self._length // 2)
247247
elif spec == 'd':
248248
return Vector(self._elem, self._length * 2)
249+
elif spec == 'N':
250+
elem = self._elem.__class__(self._elem.bitwidth() // 2)
251+
return Vector(elem, self._length * 2)
252+
elif spec == 'W':
253+
elem = self._elem.__class__(self._elem.bitwidth() * 2)
254+
return Vector(elem, self._length // 2)
249255
elif spec.startswith('x'):
250256
new_bitwidth = int(spec[1:])
251257
return Vector(self._elem, new_bitwidth // self._elem.bitwidth())
@@ -714,6 +720,8 @@ def parse_args():
714720
- 'd': double the length of the vector (u32x2 -> u32x4)
715721
- 'n': narrow the element of the vector (u32x4 -> u16x4)
716722
- 'w': widen the element of the vector (u16x4 -> u32x4)
723+
- 'N': half the length of the vector element (u32x4 -> u16x8)
724+
- 'W': double the length of the vector element (u16x8 -> u32x4)
717725
- 'u': force a number (vector or scalar) to be unsigned int (f32x4 -> u32x4)
718726
- 's': force a number (vector or scalar) to be signed int (u32x4 -> i32x4)
719727
- 'f': force a number (vector or scalar) to be float (u32x4 -> f32x4)

‎src/etc/platform-intrinsics/powerpc.json

+49
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,55 @@
7272
"llvm": "vmin{0.kind}{0.data_type_short}",
7373
"ret": "i(8-32)",
7474
"args": ["0", "0"]
75+
},
76+
{
77+
"intrinsic": "sub{0.kind}{0.data_type_short}s",
78+
"width": [128],
79+
"llvm": "vsub{0.kind}{0.data_type_short}s",
80+
"ret": "i(8-32)",
81+
"args": ["0", "0"]
82+
},
83+
{
84+
"intrinsic": "subc",
85+
"width": [128],
86+
"llvm": "vsubcuw",
87+
"ret": "u32",
88+
"args": ["0", "0"]
89+
},
90+
{
91+
"intrinsic": "add{0.kind}{0.data_type_short}s",
92+
"width": [128],
93+
"llvm": "vadd{0.kind}{0.data_type_short}s",
94+
"ret": "i(8-32)",
95+
"args": ["0", "0"]
96+
},
97+
{
98+
"intrinsic": "addc",
99+
"width": [128],
100+
"llvm": "vaddcuw",
101+
"ret": "u32",
102+
"args": ["0", "0"]
103+
},
104+
{
105+
"intrinsic": "mule{1.kind}{1.data_type_short}",
106+
"width": [128],
107+
"llvm": "vmule{0.kind}{1.data_type_short}",
108+
"ret": "i(16-32)",
109+
"args": ["0N", "1"]
110+
},
111+
{
112+
"intrinsic": "mulo{1.kind}{1.data_type_short}",
113+
"width": [128],
114+
"llvm": "vmulo{0.kind}{1.data_type_short}",
115+
"ret": "i(16-32)",
116+
"args": ["0N", "1"]
117+
},
118+
{
119+
"intrinsic": "avg{0.kind}{0.data_type_short}",
120+
"width": [128],
121+
"llvm": "vavg{0.kind}{0.data_type_short}",
122+
"ret": "i(8-32)",
123+
"args": ["0", "0"]
75124
}
76125
]
77126
}

‎src/librustc_platform_intrinsics/powerpc.rs

+140
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,146 @@ pub fn find(name: &str) -> Option<Intrinsic> {
142142
output: &::U32x4,
143143
definition: Named("llvm.ppc.altivec.vminuw")
144144
},
145+
"_vec_subsbs" => Intrinsic {
146+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
147+
output: &::I8x16,
148+
definition: Named("llvm.ppc.altivec.vsubsbs")
149+
},
150+
"_vec_sububs" => Intrinsic {
151+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
152+
output: &::U8x16,
153+
definition: Named("llvm.ppc.altivec.vsububs")
154+
},
155+
"_vec_subshs" => Intrinsic {
156+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
157+
output: &::I16x8,
158+
definition: Named("llvm.ppc.altivec.vsubshs")
159+
},
160+
"_vec_subuhs" => Intrinsic {
161+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
162+
output: &::U16x8,
163+
definition: Named("llvm.ppc.altivec.vsubuhs")
164+
},
165+
"_vec_subsws" => Intrinsic {
166+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
167+
output: &::I32x4,
168+
definition: Named("llvm.ppc.altivec.vsubsws")
169+
},
170+
"_vec_subuws" => Intrinsic {
171+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
172+
output: &::U32x4,
173+
definition: Named("llvm.ppc.altivec.vsubuws")
174+
},
175+
"_vec_subc" => Intrinsic {
176+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
177+
output: &::U32x4,
178+
definition: Named("llvm.ppc.altivec.vsubcuw")
179+
},
180+
"_vec_addsbs" => Intrinsic {
181+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
182+
output: &::I8x16,
183+
definition: Named("llvm.ppc.altivec.vaddsbs")
184+
},
185+
"_vec_addubs" => Intrinsic {
186+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
187+
output: &::U8x16,
188+
definition: Named("llvm.ppc.altivec.vaddubs")
189+
},
190+
"_vec_addshs" => Intrinsic {
191+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
192+
output: &::I16x8,
193+
definition: Named("llvm.ppc.altivec.vaddshs")
194+
},
195+
"_vec_adduhs" => Intrinsic {
196+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
197+
output: &::U16x8,
198+
definition: Named("llvm.ppc.altivec.vadduhs")
199+
},
200+
"_vec_addsws" => Intrinsic {
201+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
202+
output: &::I32x4,
203+
definition: Named("llvm.ppc.altivec.vaddsws")
204+
},
205+
"_vec_adduws" => Intrinsic {
206+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
207+
output: &::U32x4,
208+
definition: Named("llvm.ppc.altivec.vadduws")
209+
},
210+
"_vec_addc" => Intrinsic {
211+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
212+
output: &::U32x4,
213+
definition: Named("llvm.ppc.altivec.vaddcuw")
214+
},
215+
"_vec_mulesb" => Intrinsic {
216+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
217+
output: &::I16x8,
218+
definition: Named("llvm.ppc.altivec.vmulesb")
219+
},
220+
"_vec_muleub" => Intrinsic {
221+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
222+
output: &::U16x8,
223+
definition: Named("llvm.ppc.altivec.vmuleub")
224+
},
225+
"_vec_mulesh" => Intrinsic {
226+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
227+
output: &::I32x4,
228+
definition: Named("llvm.ppc.altivec.vmulesh")
229+
},
230+
"_vec_muleuh" => Intrinsic {
231+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
232+
output: &::U32x4,
233+
definition: Named("llvm.ppc.altivec.vmuleuh")
234+
},
235+
"_vec_mulosb" => Intrinsic {
236+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
237+
output: &::I16x8,
238+
definition: Named("llvm.ppc.altivec.vmulosb")
239+
},
240+
"_vec_muloub" => Intrinsic {
241+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
242+
output: &::U16x8,
243+
definition: Named("llvm.ppc.altivec.vmuloub")
244+
},
245+
"_vec_mulosh" => Intrinsic {
246+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
247+
output: &::I32x4,
248+
definition: Named("llvm.ppc.altivec.vmulosh")
249+
},
250+
"_vec_mulouh" => Intrinsic {
251+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
252+
output: &::U32x4,
253+
definition: Named("llvm.ppc.altivec.vmulouh")
254+
},
255+
"_vec_avgsb" => Intrinsic {
256+
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
257+
output: &::I8x16,
258+
definition: Named("llvm.ppc.altivec.vavgsb")
259+
},
260+
"_vec_avgub" => Intrinsic {
261+
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
262+
output: &::U8x16,
263+
definition: Named("llvm.ppc.altivec.vavgub")
264+
},
265+
"_vec_avgsh" => Intrinsic {
266+
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
267+
output: &::I16x8,
268+
definition: Named("llvm.ppc.altivec.vavgsh")
269+
},
270+
"_vec_avguh" => Intrinsic {
271+
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
272+
output: &::U16x8,
273+
definition: Named("llvm.ppc.altivec.vavguh")
274+
},
275+
"_vec_avgsw" => Intrinsic {
276+
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
277+
output: &::I32x4,
278+
definition: Named("llvm.ppc.altivec.vavgsw")
279+
},
280+
"_vec_avguw" => Intrinsic {
281+
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
282+
output: &::U32x4,
283+
definition: Named("llvm.ppc.altivec.vavguw")
284+
},
145285
_ => return None,
146286
})
147287
}

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