Docs for f16 and f128: correct a typo and add details

Author: pthariensflame

library/core/src/primitive_docs.rs

@@ -1160,7 +1160,7 @@ impl<T> (T,) {}
 ///
 /// Note that most common platforms will not support `f16` in hardware without enabling extra target
 /// features, with the notable exception of Apple Silicon (also known as M1, M2, etc.) processors.
-/// Hardware support on x86-64 requires the avx512fp16 feature, while RISC-V requires Zhf.
+/// Hardware support on x86/x86-64 requires the avx512fp16 or avx10.2 features, while RISC-V requires Zfh, and Arm/AArch64 requires FEAT_FP16.
 /// Usually the fallback implementation will be to use `f32` hardware if it exists, and convert
 /// between `f16` and `f32` when performing math.
 ///
@@ -1345,7 +1345,7 @@ mod prim_f64 {}
 ///
 /// Note that no platforms have hardware support for `f128` without enabling target specific features,
 /// as for all instruction set architectures `f128` is considered an optional feature.
-/// Only Power ISA ("PowerPC") and RISC-V specify it, and only certain microarchitectures
+/// Only Power ISA ("PowerPC") and RISC-V (via the Q extension) specify it, and only certain microarchitectures
 /// actually implement it. For x86-64 and AArch64, ISA support is not even specified,
 /// so it will always be a software implementation significantly slower than `f64`.
 ///