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matthiaskrgrmatthiaskrgr
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Rollup merge of #137804 - RalfJung:backend-repr-simd-vector, r=workingjubilee
rename BackendRepr::Vector → SimdVector For many Rustaceans, "vector" does not imply "SIMD", so let's be more clear in this type that is used pervasively in the compiler. r? `@workingjubilee`
2 parents 8c39296 + aac65f5 commit 3bf9765

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32 files changed

+92
-83
lines changed

32 files changed

+92
-83
lines changed

‎compiler/rustc_abi/src/callconv.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ impl<'a, Ty> TyAndLayout<'a, Ty> {
7474
Ok(HomogeneousAggregate::Homogeneous(Reg { kind, size: self.size }))
7575
}
7676

77-
BackendRepr::Vector { .. } => {
77+
BackendRepr::SimdVector { .. } => {
7878
assert!(!self.is_zst());
7979
Ok(HomogeneousAggregate::Homogeneous(Reg {
8080
kind: RegKind::Vector,

‎compiler/rustc_abi/src/layout.rs

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -386,13 +386,15 @@ impl<Cx: HasDataLayout> LayoutCalculator<Cx> {
386386
BackendRepr::Memory { sized: true }
387387
}
388388
// Vectors require at least element alignment, else disable the opt
389-
BackendRepr::Vector { element, count: _ } if element.align(dl).abi > align.abi => {
389+
BackendRepr::SimdVector { element, count: _ }
390+
if element.align(dl).abi > align.abi =>
391+
{
390392
BackendRepr::Memory { sized: true }
391393
}
392394
// the alignment tests passed and we can use this
393395
BackendRepr::Scalar(..)
394396
| BackendRepr::ScalarPair(..)
395-
| BackendRepr::Vector { .. }
397+
| BackendRepr::SimdVector { .. }
396398
| BackendRepr::Memory { .. } => repr,
397399
},
398400
};
@@ -464,7 +466,7 @@ impl<Cx: HasDataLayout> LayoutCalculator<Cx> {
464466
hide_niches(a);
465467
hide_niches(b);
466468
}
467-
BackendRepr::Vector { element, count: _ } => hide_niches(element),
469+
BackendRepr::SimdVector { element, count: _ } => hide_niches(element),
468470
BackendRepr::Memory { sized: _ } => {}
469471
}
470472
st.largest_niche = None;
@@ -1314,7 +1316,9 @@ impl<Cx: HasDataLayout> LayoutCalculator<Cx> {
13141316
match field.backend_repr {
13151317
// For plain scalars, or vectors of them, we can't unpack
13161318
// newtypes for `#[repr(C)]`, as that affects C ABIs.
1317-
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } if optimize_abi => {
1319+
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. }
1320+
if optimize_abi =>
1321+
{
13181322
abi = field.backend_repr;
13191323
}
13201324
// But scalar pairs are Rust-specific and get

‎compiler/rustc_abi/src/layout/ty.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,7 @@ impl<'a, Ty> TyAndLayout<'a, Ty> {
219219
C: HasDataLayout,
220220
{
221221
match self.backend_repr {
222-
BackendRepr::Vector { .. } => self.size == expected_size,
222+
BackendRepr::SimdVector { .. } => self.size == expected_size,
223223
BackendRepr::Memory { .. } => {
224224
if self.fields.count() == 1 && self.fields.offset(0).bytes() == 0 {
225225
self.field(cx, 0).is_single_vector_element(cx, expected_size)

‎compiler/rustc_abi/src/lib.rs

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1410,7 +1410,7 @@ impl AddressSpace {
14101410
pub enum BackendRepr {
14111411
Scalar(Scalar),
14121412
ScalarPair(Scalar, Scalar),
1413-
Vector {
1413+
SimdVector {
14141414
element: Scalar,
14151415
count: u64,
14161416
},
@@ -1426,9 +1426,9 @@ impl BackendRepr {
14261426
#[inline]
14271427
pub fn is_unsized(&self) -> bool {
14281428
match *self {
1429-
BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) | BackendRepr::Vector { .. } => {
1430-
false
1431-
}
1429+
BackendRepr::Scalar(_)
1430+
| BackendRepr::ScalarPair(..)
1431+
| BackendRepr::SimdVector { .. } => false,
14321432
BackendRepr::Memory { sized } => !sized,
14331433
}
14341434
}
@@ -1467,7 +1467,7 @@ impl BackendRepr {
14671467
BackendRepr::Scalar(s) => Some(s.align(cx).abi),
14681468
BackendRepr::ScalarPair(s1, s2) => Some(s1.align(cx).max(s2.align(cx)).abi),
14691469
// The align of a Vector can vary in surprising ways
1470-
BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => None,
1470+
BackendRepr::SimdVector { .. } | BackendRepr::Memory { .. } => None,
14711471
}
14721472
}
14731473

@@ -1489,7 +1489,7 @@ impl BackendRepr {
14891489
Some(size)
14901490
}
14911491
// The size of a Vector can vary in surprising ways
1492-
BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => None,
1492+
BackendRepr::SimdVector { .. } | BackendRepr::Memory { .. } => None,
14931493
}
14941494
}
14951495

@@ -1500,8 +1500,8 @@ impl BackendRepr {
15001500
BackendRepr::ScalarPair(s1, s2) => {
15011501
BackendRepr::ScalarPair(s1.to_union(), s2.to_union())
15021502
}
1503-
BackendRepr::Vector { element, count } => {
1504-
BackendRepr::Vector { element: element.to_union(), count }
1503+
BackendRepr::SimdVector { element, count } => {
1504+
BackendRepr::SimdVector { element: element.to_union(), count }
15051505
}
15061506
BackendRepr::Memory { .. } => BackendRepr::Memory { sized: true },
15071507
}
@@ -1513,8 +1513,8 @@ impl BackendRepr {
15131513
// We do *not* ignore the sign since it matters for some ABIs (e.g. s390x).
15141514
(BackendRepr::Scalar(l), BackendRepr::Scalar(r)) => l.primitive() == r.primitive(),
15151515
(
1516-
BackendRepr::Vector { element: element_l, count: count_l },
1517-
BackendRepr::Vector { element: element_r, count: count_r },
1516+
BackendRepr::SimdVector { element: element_l, count: count_l },
1517+
BackendRepr::SimdVector { element: element_r, count: count_r },
15181518
) => element_l.primitive() == element_r.primitive() && count_l == count_r,
15191519
(BackendRepr::ScalarPair(l1, l2), BackendRepr::ScalarPair(r1, r2)) => {
15201520
l1.primitive() == r1.primitive() && l2.primitive() == r2.primitive()
@@ -1735,7 +1735,7 @@ impl<FieldIdx: Idx, VariantIdx: Idx> LayoutData<FieldIdx, VariantIdx> {
17351735
/// Returns `true` if this is an aggregate type (including a ScalarPair!)
17361736
pub fn is_aggregate(&self) -> bool {
17371737
match self.backend_repr {
1738-
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => false,
1738+
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => false,
17391739
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => true,
17401740
}
17411741
}
@@ -1877,9 +1877,9 @@ impl<FieldIdx: Idx, VariantIdx: Idx> LayoutData<FieldIdx, VariantIdx> {
18771877
/// non-trivial alignment constraints. You probably want to use `is_1zst` instead.
18781878
pub fn is_zst(&self) -> bool {
18791879
match self.backend_repr {
1880-
BackendRepr::Scalar(_) | BackendRepr::ScalarPair(..) | BackendRepr::Vector { .. } => {
1881-
false
1882-
}
1880+
BackendRepr::Scalar(_)
1881+
| BackendRepr::ScalarPair(..)
1882+
| BackendRepr::SimdVector { .. } => false,
18831883
BackendRepr::Memory { sized } => sized && self.size.bytes() == 0,
18841884
}
18851885
}

‎compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ impl<'tcx> ArgAbiExt<'tcx> for ArgAbi<'tcx, Ty<'tcx>> {
8484
AbiParam::new(scalar_to_clif_type(tcx, scalar)),
8585
attrs
8686
)],
87-
BackendRepr::Vector { .. } => {
87+
BackendRepr::SimdVector { .. } => {
8888
let vector_ty = crate::intrinsics::clif_vector_type(tcx, self.layout);
8989
smallvec![AbiParam::new(vector_ty)]
9090
}
@@ -135,7 +135,7 @@ impl<'tcx> ArgAbiExt<'tcx> for ArgAbi<'tcx, Ty<'tcx>> {
135135
BackendRepr::Scalar(scalar) => {
136136
(None, vec![AbiParam::new(scalar_to_clif_type(tcx, scalar))])
137137
}
138-
BackendRepr::Vector { .. } => {
138+
BackendRepr::SimdVector { .. } => {
139139
let vector_ty = crate::intrinsics::clif_vector_type(tcx, self.layout);
140140
(None, vec![AbiParam::new(vector_ty)])
141141
}

‎compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ fn report_atomic_type_validation_error<'tcx>(
5353

5454
pub(crate) fn clif_vector_type<'tcx>(tcx: TyCtxt<'tcx>, layout: TyAndLayout<'tcx>) -> Type {
5555
let (element, count) = match layout.backend_repr {
56-
BackendRepr::Vector { element, count } => (element, count),
56+
BackendRepr::SimdVector { element, count } => (element, count),
5757
_ => unreachable!(),
5858
};
5959

‎compiler/rustc_codegen_cranelift/src/value_and_place.rs

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -173,9 +173,11 @@ impl<'tcx> CValue<'tcx> {
173173
CValueInner::ByRef(ptr, None) => {
174174
let clif_ty = match layout.backend_repr {
175175
BackendRepr::Scalar(scalar) => scalar_to_clif_type(fx.tcx, scalar),
176-
BackendRepr::Vector { element, count } => scalar_to_clif_type(fx.tcx, element)
177-
.by(u32::try_from(count).unwrap())
178-
.unwrap(),
176+
BackendRepr::SimdVector { element, count } => {
177+
scalar_to_clif_type(fx.tcx, element)
178+
.by(u32::try_from(count).unwrap())
179+
.unwrap()
180+
}
179181
_ => unreachable!("{:?}", layout.ty),
180182
};
181183
let mut flags = MemFlags::new();

‎compiler/rustc_codegen_gcc/src/intrinsic/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc
312312
let layout = self.layout_of(tp_ty).layout;
313313
let _use_integer_compare = match layout.backend_repr() {
314314
Scalar(_) | ScalarPair(_, _) => true,
315-
Vector { .. } => false,
315+
SimdVector { .. } => false,
316316
Memory { .. } => {
317317
// For rusty ABIs, small aggregates are actually passed
318318
// as `RegKind::Integer` (see `FnAbi::adjust_for_abi`),

‎compiler/rustc_codegen_gcc/src/type_of.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ fn uncached_gcc_type<'gcc, 'tcx>(
6363
) -> Type<'gcc> {
6464
match layout.backend_repr {
6565
BackendRepr::Scalar(_) => bug!("handled elsewhere"),
66-
BackendRepr::Vector { ref element, count } => {
66+
BackendRepr::SimdVector { ref element, count } => {
6767
let element = layout.scalar_gcc_type_at(cx, element, Size::ZERO);
6868
let element =
6969
// NOTE: gcc doesn't allow pointer types in vectors.
@@ -178,17 +178,17 @@ pub trait LayoutGccExt<'tcx> {
178178
impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> {
179179
fn is_gcc_immediate(&self) -> bool {
180180
match self.backend_repr {
181-
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => true,
181+
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => true,
182182
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => false,
183183
}
184184
}
185185

186186
fn is_gcc_scalar_pair(&self) -> bool {
187187
match self.backend_repr {
188188
BackendRepr::ScalarPair(..) => true,
189-
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => {
190-
false
191-
}
189+
BackendRepr::Scalar(_)
190+
| BackendRepr::SimdVector { .. }
191+
| BackendRepr::Memory { .. } => false,
192192
}
193193
}
194194

‎compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 21 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -939,9 +939,10 @@ fn llvm_fixup_input<'ll, 'tcx>(
939939
}
940940
bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
941941
}
942-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
943-
if layout.size.bytes() == 8 =>
944-
{
942+
(
943+
AArch64(AArch64InlineAsmRegClass::vreg_low16),
944+
BackendRepr::SimdVector { element, count },
945+
) if layout.size.bytes() == 8 => {
945946
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
946947
let vec_ty = bx.cx.type_vector(elem_ty, count);
947948
let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
@@ -954,7 +955,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
954955
}
955956
(
956957
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
957-
BackendRepr::Vector { .. },
958+
BackendRepr::SimdVector { .. },
958959
) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
959960
(
960961
X86(
@@ -989,7 +990,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
989990
| X86InlineAsmRegClass::ymm_reg
990991
| X86InlineAsmRegClass::zmm_reg,
991992
),
992-
BackendRepr::Vector { element, count: count @ (8 | 16) },
993+
BackendRepr::SimdVector { element, count: count @ (8 | 16) },
993994
) if element.primitive() == Primitive::Float(Float::F16) => {
994995
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
995996
}
@@ -1026,7 +1027,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
10261027
| ArmInlineAsmRegClass::qreg_low4
10271028
| ArmInlineAsmRegClass::qreg_low8,
10281029
),
1029-
BackendRepr::Vector { element, count: count @ (4 | 8) },
1030+
BackendRepr::SimdVector { element, count: count @ (4 | 8) },
10301031
) if element.primitive() == Primitive::Float(Float::F16) => {
10311032
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
10321033
}
@@ -1099,9 +1100,10 @@ fn llvm_fixup_output<'ll, 'tcx>(
10991100
}
11001101
value
11011102
}
1102-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
1103-
if layout.size.bytes() == 8 =>
1104-
{
1103+
(
1104+
AArch64(AArch64InlineAsmRegClass::vreg_low16),
1105+
BackendRepr::SimdVector { element, count },
1106+
) if layout.size.bytes() == 8 => {
11051107
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
11061108
let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
11071109
let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
@@ -1114,7 +1116,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
11141116
}
11151117
(
11161118
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
1117-
BackendRepr::Vector { .. },
1119+
BackendRepr::SimdVector { .. },
11181120
) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
11191121
(
11201122
X86(
@@ -1145,7 +1147,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
11451147
| X86InlineAsmRegClass::ymm_reg
11461148
| X86InlineAsmRegClass::zmm_reg,
11471149
),
1148-
BackendRepr::Vector { element, count: count @ (8 | 16) },
1150+
BackendRepr::SimdVector { element, count: count @ (8 | 16) },
11491151
) if element.primitive() == Primitive::Float(Float::F16) => {
11501152
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
11511153
}
@@ -1182,7 +1184,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
11821184
| ArmInlineAsmRegClass::qreg_low4
11831185
| ArmInlineAsmRegClass::qreg_low8,
11841186
),
1185-
BackendRepr::Vector { element, count: count @ (4 | 8) },
1187+
BackendRepr::SimdVector { element, count: count @ (4 | 8) },
11861188
) if element.primitive() == Primitive::Float(Float::F16) => {
11871189
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
11881190
}
@@ -1243,9 +1245,10 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12431245
let count = 16 / layout.size.bytes();
12441246
cx.type_vector(elem_ty, count)
12451247
}
1246-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
1247-
if layout.size.bytes() == 8 =>
1248-
{
1248+
(
1249+
AArch64(AArch64InlineAsmRegClass::vreg_low16),
1250+
BackendRepr::SimdVector { element, count },
1251+
) if layout.size.bytes() == 8 => {
12491252
let elem_ty = llvm_asm_scalar_type(cx, element);
12501253
cx.type_vector(elem_ty, count * 2)
12511254
}
@@ -1256,7 +1259,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12561259
}
12571260
(
12581261
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
1259-
BackendRepr::Vector { .. },
1262+
BackendRepr::SimdVector { .. },
12601263
) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
12611264
(
12621265
X86(
@@ -1284,7 +1287,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12841287
| X86InlineAsmRegClass::ymm_reg
12851288
| X86InlineAsmRegClass::zmm_reg,
12861289
),
1287-
BackendRepr::Vector { element, count: count @ (8 | 16) },
1290+
BackendRepr::SimdVector { element, count: count @ (8 | 16) },
12881291
) if element.primitive() == Primitive::Float(Float::F16) => {
12891292
cx.type_vector(cx.type_i16(), count)
12901293
}
@@ -1321,7 +1324,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
13211324
| ArmInlineAsmRegClass::qreg_low4
13221325
| ArmInlineAsmRegClass::qreg_low8,
13231326
),
1324-
BackendRepr::Vector { element, count: count @ (4 | 8) },
1327+
BackendRepr::SimdVector { element, count: count @ (4 | 8) },
13251328
) if element.primitive() == Primitive::Float(Float::F16) => {
13261329
cx.type_vector(cx.type_i16(), count)
13271330
}

‎compiler/rustc_codegen_llvm/src/intrinsic.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -470,7 +470,7 @@ impl<'ll, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
470470
let layout = self.layout_of(tp_ty).layout;
471471
let use_integer_compare = match layout.backend_repr() {
472472
Scalar(_) | ScalarPair(_, _) => true,
473-
Vector { .. } => false,
473+
SimdVector { .. } => false,
474474
Memory { .. } => {
475475
// For rusty ABIs, small aggregates are actually passed
476476
// as `RegKind::Integer` (see `FnAbi::adjust_for_abi`),

‎compiler/rustc_codegen_llvm/src/type_of.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ fn uncached_llvm_type<'a, 'tcx>(
1919
) -> &'a Type {
2020
match layout.backend_repr {
2121
BackendRepr::Scalar(_) => bug!("handled elsewhere"),
22-
BackendRepr::Vector { element, count } => {
22+
BackendRepr::SimdVector { element, count } => {
2323
let element = layout.scalar_llvm_type_at(cx, element);
2424
return cx.type_vector(element, count);
2525
}
@@ -171,17 +171,17 @@ pub(crate) trait LayoutLlvmExt<'tcx> {
171171
impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
172172
fn is_llvm_immediate(&self) -> bool {
173173
match self.backend_repr {
174-
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => true,
174+
BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => true,
175175
BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => false,
176176
}
177177
}
178178

179179
fn is_llvm_scalar_pair(&self) -> bool {
180180
match self.backend_repr {
181181
BackendRepr::ScalarPair(..) => true,
182-
BackendRepr::Scalar(_) | BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => {
183-
false
184-
}
182+
BackendRepr::Scalar(_)
183+
| BackendRepr::SimdVector { .. }
184+
| BackendRepr::Memory { .. } => false,
185185
}
186186
}
187187

‎compiler/rustc_codegen_ssa/src/mir/naked_asm.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -349,7 +349,7 @@ fn wasm_type<'tcx>(
349349
PassMode::Direct(_) => {
350350
let direct_type = match arg_abi.layout.backend_repr {
351351
BackendRepr::Scalar(scalar) => wasm_primitive(scalar.primitive(), ptr_type),
352-
BackendRepr::Vector { .. } => "v128",
352+
BackendRepr::SimdVector { .. } => "v128",
353353
BackendRepr::Memory { .. } => {
354354
// FIXME: remove this branch once the wasm32-unknown-unknown ABI is fixed
355355
let _ = WasmCAbi::Legacy;

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