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Define x86 fused multiply-add intrinsics
This defines the following intrinsics for 128 and 256 bit vectors of f32 and f64: * `fmadd` * `fmaddsub` * `fmsub` * `fmsubadd` * `fnmadd` * `fnmsub` The `_sd` and `_ss` variants are not included yet. Intel intrinsic reference: https://software.intel.com/en-us/node/523929 The intrinsics there are listed under AVX2, but in the Intel Intrinsic Guide they are part of the "FMA" technology, and LLVM puts them under FMA, not AVX2.
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{
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"llvm_prefix": "llvm.x86.fma.",
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"intrinsics": [
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{
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"intrinsic": "{0.width_mm}_fmadd_{0.data_type}",
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"width": [128, 256],
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"llvm": "vfmadd.{0.data_type_short}{0.width_suffix}",
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"ret": "f(32-64)",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "{0.width_mm}_fmaddsub_{0.data_type}",
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"width": [128, 256],
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"llvm": "vfmaddsub.{0.data_type_short}{0.width_suffix}",
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"ret": "f(32-64)",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "{0.width_mm}_fmsub_{0.data_type}",
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"width": [128, 256],
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"llvm": "vfmsub.{0.data_type_short}{0.width_suffix}",
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"ret": "f(32-64)",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "{0.width_mm}_fmsubadd_{0.data_type}",
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"width": [128, 256],
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"llvm": "vfmsubadd.{0.data_type_short}{0.width_suffix}",
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"ret": "f(32-64)",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "{0.width_mm}_fnmadd_{0.data_type}",
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"width": [128, 256],
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"llvm": "vfnmadd.{0.data_type_short}{0.width_suffix}",
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"ret": "f(32-64)",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "{0.width_mm}_fnmsub_{0.data_type}",
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"width": [128, 256],
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"llvm": "vfnmsub.{0.data_type_short}{0.width_suffix}",
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"ret": "f(32-64)",
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"args": ["0", "0", "0"]
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}
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]
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}

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