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| 1 | +# `asm_experimental_arch` |
| 2 | + |
| 3 | +The tracking issue for this feature is: [#72016] |
| 4 | + |
| 5 | +[#72016]: https://github.com/rust-lang/rust/issues/72016 |
| 6 | + |
| 7 | +------------------------ |
| 8 | + |
| 9 | +This feature tracks `asm!` and `global_asm!` support for the following architectures: |
| 10 | +- NVPTX |
| 11 | +- PowerPC |
| 12 | +- Hexagon |
| 13 | +- MIPS32r2 and MIPS64r2 |
| 14 | +- wasm32 |
| 15 | +- BPF |
| 16 | +- SPIR-V |
| 17 | +- AVR |
| 18 | + |
| 19 | +## Register classes |
| 20 | + |
| 21 | +| Architecture | Register class | Registers | LLVM constraint code | |
| 22 | +| ------------ | -------------- | ---------------------------------- | -------------------- | |
| 23 | +| MIPS | `reg` | `$[2-25]` | `r` | |
| 24 | +| MIPS | `freg` | `$f[0-31]` | `f` | |
| 25 | +| NVPTX | `reg16` | None\* | `h` | |
| 26 | +| NVPTX | `reg32` | None\* | `r` | |
| 27 | +| NVPTX | `reg64` | None\* | `l` | |
| 28 | +| Hexagon | `reg` | `r[0-28]` | `r` | |
| 29 | +| PowerPC | `reg` | `r[0-31]` | `r` | |
| 30 | +| PowerPC | `reg_nonzero` | `r[1-31]` | `b` | |
| 31 | +| PowerPC | `freg` | `f[0-31]` | `f` | |
| 32 | +| PowerPC | `cr` | `cr[0-7]`, `cr` | Only clobbers | |
| 33 | +| PowerPC | `xer` | `xer` | Only clobbers | |
| 34 | +| wasm32 | `local` | None\* | `r` | |
| 35 | +| BPF | `reg` | `r[0-10]` | `r` | |
| 36 | +| BPF | `wreg` | `w[0-10]` | `w` | |
| 37 | +| AVR | `reg` | `r[2-25]`, `XH`, `XL`, `ZH`, `ZL` | `r` | |
| 38 | +| AVR | `reg_upper` | `r[16-25]`, `XH`, `XL`, `ZH`, `ZL` | `d` | |
| 39 | +| AVR | `reg_pair` | `r3r2` .. `r25r24`, `X`, `Z` | `r` | |
| 40 | +| AVR | `reg_iw` | `r25r24`, `X`, `Z` | `w` | |
| 41 | +| AVR | `reg_ptr` | `X`, `Z` | `e` | |
| 42 | + |
| 43 | +> **Notes**: |
| 44 | +> - NVPTX doesn't have a fixed register set, so named registers are not supported. |
| 45 | +> |
| 46 | +> - WebAssembly doesn't have registers, so named registers are not supported. |
| 47 | +
|
| 48 | +# Register class supported types |
| 49 | + |
| 50 | +| Architecture | Register class | Target feature | Allowed types | |
| 51 | +| ------------ | ------------------------------- | -------------- | --------------------------------------- | |
| 52 | +| MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` | |
| 53 | +| MIPS32 | `freg` | None | `f32`, `f64` | |
| 54 | +| MIPS64 | `reg` | None | `i8`, `i16`, `i32`, `i64`, `f32`, `f64` | |
| 55 | +| MIPS64 | `freg` | None | `f32`, `f64` | |
| 56 | +| NVPTX | `reg16` | None | `i8`, `i16` | |
| 57 | +| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` | |
| 58 | +| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` | |
| 59 | +| Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` | |
| 60 | +| PowerPC | `reg` | None | `i8`, `i16`, `i32` | |
| 61 | +| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32` | |
| 62 | +| PowerPC | `freg` | None | `f32`, `f64` | |
| 63 | +| PowerPC | `cr` | N/A | Only clobbers | |
| 64 | +| PowerPC | `xer` | N/A | Only clobbers | |
| 65 | +| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` | |
| 66 | +| BPF | `reg` | None | `i8` `i16` `i32` `i64` | |
| 67 | +| BPF | `wreg` | `alu32` | `i8` `i16` `i32` | |
| 68 | +| AVR | `reg`, `reg_upper` | None | `i8` | |
| 69 | +| AVR | `reg_pair`, `reg_iw`, `reg_ptr` | None | `i16` | |
| 70 | + |
| 71 | +## Register aliases |
| 72 | + |
| 73 | +| Architecture | Base register | Aliases | |
| 74 | +| ------------ | ------------- | --------- | |
| 75 | +| Hexagon | `r29` | `sp` | |
| 76 | +| Hexagon | `r30` | `fr` | |
| 77 | +| Hexagon | `r31` | `lr` | |
| 78 | +| BPF | `r[0-10]` | `w[0-10]` | |
| 79 | +| AVR | `XH` | `r27` | |
| 80 | +| AVR | `XL` | `r26` | |
| 81 | +| AVR | `ZH` | `r31` | |
| 82 | +| AVR | `ZL` | `r30` | |
| 83 | + |
| 84 | +## Unsupported registers |
| 85 | + |
| 86 | +| Architecture | Unsupported register | Reason | |
| 87 | +| ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | |
| 88 | +| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. | |
| 89 | +| All | `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR) | The frame pointer cannot be used as an input or output. | |
| 90 | +| All | `r19` (Hexagon) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. | |
| 91 | +| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. | |
| 92 | +| MIPS | `$1` or `$at` | Reserved for assembler. | |
| 93 | +| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. | |
| 94 | +| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. | |
| 95 | +| MIPS | `$ra` | Return address cannot be used as inputs or outputs. | |
| 96 | +| Hexagon | `lr` | This is the link register which cannot be used as an input or output. | |
| 97 | +| AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. | |
| 98 | + |
| 99 | +## Template modifiers |
| 100 | + |
| 101 | +| Architecture | Register class | Modifier | Example output | LLVM modifier | |
| 102 | +| ------------ | -------------- | -------- | -------------- | ------------- | |
| 103 | +| MIPS | `reg` | None | `$2` | None | |
| 104 | +| MIPS | `freg` | None | `$f0` | None | |
| 105 | +| NVPTX | `reg16` | None | `rs0` | None | |
| 106 | +| NVPTX | `reg32` | None | `r0` | None | |
| 107 | +| NVPTX | `reg64` | None | `rd0` | None | |
| 108 | +| Hexagon | `reg` | None | `r0` | None | |
| 109 | +| PowerPC | `reg` | None | `0` | None | |
| 110 | +| PowerPC | `reg_nonzero` | None | `3` | `b` | |
| 111 | +| PowerPC | `freg` | None | `0` | None | |
| 112 | + |
| 113 | +# Flags covered by `preserves_flags` |
| 114 | + |
| 115 | +These flags registers must be restored upon exiting the asm block if the `preserves_flags` option is set: |
| 116 | +- AVR |
| 117 | + - The status register `SREG`. |
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