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Add SwitchTargetValue.
This is much clearer than `Option<u128>`.
1 parent e1362ca commit e90dfc9

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5 files changed

+35
-12
lines changed

5 files changed

+35
-12
lines changed

compiler/rustc_middle/src/mir/basic_blocks.rs

+12-4
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,9 @@ use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
99
use smallvec::SmallVec;
1010

1111
use crate::mir::traversal::Postorder;
12-
use crate::mir::{BasicBlock, BasicBlockData, START_BLOCK, Terminator, TerminatorKind};
12+
use crate::mir::{
13+
BasicBlock, BasicBlockData, START_BLOCK, SwitchTargetValue, Terminator, TerminatorKind,
14+
};
1315

1416
#[derive(Clone, TyEncodable, TyDecodable, Debug, HashStable, TypeFoldable, TypeVisitable)]
1517
pub struct BasicBlocks<'tcx> {
@@ -28,7 +30,7 @@ type Predecessors = IndexVec<BasicBlock, SmallVec<[BasicBlock; 4]>>;
2830
/// `BasicBlocks::switch_sources`, which is only called by backwards analyses
2931
/// that do `SwitchInt` handling, and we don't have any of those, not even in
3032
/// tests. See #95120 and #94576.
31-
type SwitchSources = FxHashMap<(BasicBlock, BasicBlock), SmallVec<[Option<u128>; 1]>>;
33+
type SwitchSources = FxHashMap<(BasicBlock, BasicBlock), SmallVec<[SwitchTargetValue; 1]>>;
3234

3335
#[derive(Clone, Default, Debug)]
3436
struct Cache {
@@ -90,9 +92,15 @@ impl<'tcx> BasicBlocks<'tcx> {
9092
}) = &data.terminator
9193
{
9294
for (value, target) in targets.iter() {
93-
switch_sources.entry((target, bb)).or_default().push(Some(value));
95+
switch_sources
96+
.entry((target, bb))
97+
.or_default()
98+
.push(SwitchTargetValue::Normal(value));
9499
}
95-
switch_sources.entry((targets.otherwise(), bb)).or_default().push(None);
100+
switch_sources
101+
.entry((targets.otherwise(), bb))
102+
.or_default()
103+
.push(SwitchTargetValue::Otherwise);
96104
}
97105
}
98106
switch_sources

compiler/rustc_middle/src/mir/syntax.rs

+8
Original file line numberDiff line numberDiff line change
@@ -1013,6 +1013,14 @@ impl TerminatorKind<'_> {
10131013
}
10141014
}
10151015

1016+
#[derive(Debug, Clone, Copy)]
1017+
pub enum SwitchTargetValue {
1018+
// A normal switch value.
1019+
Normal(u128),
1020+
// The final "otherwise" fallback value.
1021+
Otherwise,
1022+
}
1023+
10161024
#[derive(Debug, Clone, TyEncodable, TyDecodable, Hash, HashStable, PartialEq)]
10171025
pub struct SwitchTargets {
10181026
/// Possible values. The locations to branch to in each case

compiler/rustc_mir_dataflow/src/framework/direction.rs

+6-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
use std::ops::RangeInclusive;
22

3-
use rustc_middle::mir::{self, BasicBlock, CallReturnPlaces, Location, TerminatorEdges};
3+
use rustc_middle::mir::{
4+
self, BasicBlock, CallReturnPlaces, Location, SwitchTargetValue, TerminatorEdges,
5+
};
46

57
use super::visitor::ResultsVisitor;
68
use super::{Analysis, Effect, EffectIndex, Results, SwitchIntTarget};
@@ -290,7 +292,8 @@ impl Direction for Forward {
290292
let mut tmp = analysis.bottom_value(body);
291293
for (value, target) in targets.iter() {
292294
tmp.clone_from(exit_state);
293-
let si_target = SwitchIntTarget { value: Some(value), target };
295+
let si_target =
296+
SwitchIntTarget { value: SwitchTargetValue::Normal(value), target };
294297
analysis.apply_switch_int_edge_effect(&mut data, &mut tmp, si_target);
295298
propagate(target, &tmp);
296299
}
@@ -302,7 +305,7 @@ impl Direction for Forward {
302305
analysis.apply_switch_int_edge_effect(
303306
&mut data,
304307
exit_state,
305-
SwitchIntTarget { value: None, target: otherwise },
308+
SwitchIntTarget { value: SwitchTargetValue::Otherwise, target: otherwise },
306309
);
307310
propagate(otherwise, exit_state);
308311
} else {

compiler/rustc_mir_dataflow/src/framework/mod.rs

+4-2
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,9 @@ use rustc_data_structures::work_queue::WorkQueue;
3838
use rustc_index::bit_set::{DenseBitSet, MixedBitSet};
3939
use rustc_index::{Idx, IndexVec};
4040
use rustc_middle::bug;
41-
use rustc_middle::mir::{self, BasicBlock, CallReturnPlaces, Location, TerminatorEdges, traversal};
41+
use rustc_middle::mir::{
42+
self, BasicBlock, CallReturnPlaces, Location, SwitchTargetValue, TerminatorEdges, traversal,
43+
};
4244
use rustc_middle::ty::TyCtxt;
4345
use tracing::error;
4446

@@ -431,7 +433,7 @@ impl EffectIndex {
431433
}
432434

433435
pub struct SwitchIntTarget {
434-
pub value: Option<u128>,
436+
pub value: SwitchTargetValue,
435437
pub target: BasicBlock,
436438
}
437439

compiler/rustc_mir_dataflow/src/impls/initialized.rs

+5-3
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,9 @@ use rustc_abi::VariantIdx;
44
use rustc_index::Idx;
55
use rustc_index::bit_set::{DenseBitSet, MixedBitSet};
66
use rustc_middle::bug;
7-
use rustc_middle::mir::{self, Body, CallReturnPlaces, Location, TerminatorEdges};
7+
use rustc_middle::mir::{
8+
self, Body, CallReturnPlaces, Location, SwitchTargetValue, TerminatorEdges,
9+
};
810
use rustc_middle::ty::util::Discr;
911
use rustc_middle::ty::{self, TyCtxt};
1012
use tracing::{debug, instrument};
@@ -424,7 +426,7 @@ impl<'tcx> Analysis<'tcx> for MaybeInitializedPlaces<'_, 'tcx> {
424426
state: &mut Self::Domain,
425427
edge: SwitchIntTarget,
426428
) {
427-
if let Some(value) = edge.value {
429+
if let SwitchTargetValue::Normal(value) = edge.value {
428430
// Kill all move paths that correspond to variants we know to be inactive along this
429431
// particular outgoing edge of a `SwitchInt`.
430432
drop_flag_effects::on_all_inactive_variants(
@@ -537,7 +539,7 @@ impl<'tcx> Analysis<'tcx> for MaybeUninitializedPlaces<'_, 'tcx> {
537539
state: &mut Self::Domain,
538540
edge: SwitchIntTarget,
539541
) {
540-
if let Some(value) = edge.value {
542+
if let SwitchTargetValue::Normal(value) = edge.value {
541543
// Mark all move paths that correspond to variants other than this one as maybe
542544
// uninitialized (in reality, they are *definitely* uninitialized).
543545
drop_flag_effects::on_all_inactive_variants(

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