riscv: hypervisor load and store instructions

adds `riscv64` module

Author: luojia65

crates/core_arch/src/mod.rs

@@ -66,6 +66,17 @@ pub mod arch {
         pub use crate::core_arch::riscv::*;
     }
 
+    /// Platform-specific intrinsics for the `riscv64` platform.
+    ///
+    /// See the [module documentation](../index.html) for more details.
+    #[cfg(any(target_arch = "riscv64", doc))]
+    #[doc(cfg(any(target_arch = "riscv64")))]
+    #[unstable(feature = "stdsimd", issue = "27731")]
+    pub mod riscv64 {
+        pub use crate::core_arch::riscv::*;
+        pub use crate::core_arch::riscv64::*;
+    }
+
     /// Platform-specific intrinsics for the `wasm32` platform.
     ///
     /// This module provides intrinsics specific to the WebAssembly
@@ -266,6 +277,10 @@ mod arm;
 #[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))]
 mod riscv;
 
+#[cfg(any(target_arch = "riscv64", doc))]
+#[doc(cfg(any(target_arch = "riscv64")))]
+mod riscv64;
+
 #[cfg(any(target_family = "wasm", doc))]
 #[doc(cfg(target_family = "wasm"))]
 mod wasm32;

crates/core_arch/src/riscv/mod.rs

@@ -143,3 +143,167 @@ pub unsafe fn sfence_w_inval() {
 pub unsafe fn sfence_inval_ir() {
     asm!(".insn i 0x73, 0, x0, x0, 0x181")
 }
+
+/// Loads memory from hypervisor by signed byte integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.B` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_b(src: *const i8) -> i8 {
+    let value: i8;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x600", out(reg) value, in(reg) src);
+    value
+}
+
+/// Loads memory from hypervisor by unsigned byte integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.BU` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_bu(src: *const u8) -> u8 {
+    let value: u8;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x601", out(reg) value, in(reg) src);
+    value
+}
+
+/// Loads memory from hypervisor by signed half integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.H` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_h(src: *const i16) -> i16 {
+    let value: i16;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x640", out(reg) value, in(reg) src);
+    value
+}
+
+/// Loads memory from hypervisor by unsigned half integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.HU` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_hu(src: *const u16) -> u16 {
+    let value: u16;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x641", out(reg) value, in(reg) src);
+    value
+}
+
+/// Accesses instruction from hypervisor by unsigned half integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// the memory being read must be executable in both stages of address translation,
+/// but read permission is not required.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLVX.HU` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlvx_hu(src: *const u16) -> u16 {
+    let insn: u16;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x643", out(reg) insn, in(reg) src);
+    insn
+}
+
+/// Loads memory from hypervisor by signed word integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.W` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_w(src: *const i32) -> i32 {
+    let value: i32;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x680", out(reg) value, in(reg) src);
+    value
+}
+
+/// Accesses instruction from hypervisor by unsigned word integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// the memory being read must be executable in both stages of address translation,
+/// but read permission is not required.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLVX.WU` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlvx_wu(src: *const u32) -> u32 {
+    let insn: u32;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x683", out(reg) insn, in(reg) src);
+    insn
+}
+
+/// Stores memory from hypervisor by byte integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HSV.B` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hsv_b(dst: *mut i8, src: i8) {
+    asm!(".insn r 0x73, 0x4, 0x31, x0, {}, {}", in(reg) dst, in(reg) src);
+}
+
+/// Stores memory from hypervisor by half integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HSV.H` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hsv_h(dst: *mut i16, src: i16) {
+    asm!(".insn r 0x73, 0x4, 0x33, x0, {}, {}", in(reg) dst, in(reg) src);
+}
+
+/// Stores memory from hypervisor by word integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HSV.W` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hsv_w(dst: *mut i32, src: i32) {
+    asm!(".insn r 0x73, 0x4, 0x35, x0, {}, {}", in(reg) dst, in(reg) src);
+}

crates/core_arch/src/riscv64/mod.rs

@@ -0,0 +1,55 @@
+//! RISC-V RV64 specific intrinsics
+use crate::arch::asm;
+
+/// Loads memory from hypervisor by unsigned word integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// This operation is not available under RV32 base instruction set.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.WU` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_wu(src: *const u32) -> u32 {
+    let value: u32;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x681", out(reg) value, in(reg) src);
+    value
+}
+
+/// Loads memory from hypervisor by unsigned double integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// This operation is not available under RV32 base instruction set.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HLV.D` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hlv_d(src: *const i64) -> i64 {
+    let value: i64;
+    asm!(".insn i 0x73, 0x4, {}, {}, 0x6C0", out(reg) value, in(reg) src);
+    value
+}
+
+/// Stores memory from hypervisor by double integer
+///
+/// This instruction performs an explicit memory access as though `V=1`;
+/// i.e., with the address translation and protection, and the endianness, that apply to memory
+/// accesses in either VS-mode or VU-mode.
+///
+/// # Unsafety
+///
+/// This function accesses the virtual supervisor or user via a `HSV.D` instruction which is effectively
+/// an unreference to any memory address, thus is wrapped into an unsafe function.
+#[inline]
+pub unsafe fn hsv_d(dst: *mut i64, src: i64) {
+    asm!(".insn r 0x73, 0x4, 0x37, x0, {}, {}", in(reg) dst, in(reg) src);
+}