@@ -53,13 +53,13 @@ pub(crate) fn detect_features() -> cache::Initializer {
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) ;
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}
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- parse_system_registers ( aa64isar0, aa64isar1, aa64pfr0)
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+ parse_system_registers ( aa64isar0, aa64isar1, Some ( aa64pfr0) )
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}
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pub ( crate ) fn parse_system_registers (
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aa64isar0 : u64 ,
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aa64isar1 : u64 ,
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- aa64pfr0 : u64 ,
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+ aa64pfr0 : Option < u64 > ,
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) -> cache:: Initializer {
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let mut value = cache:: Initializer :: default ( ) ;
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@@ -76,26 +76,28 @@ pub(crate) fn parse_system_registers(
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enable_feature ( Feature :: crc, bits_shift ( aa64isar0, 19 , 16 ) >= 1 ) ;
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// ID_AA64PFR0_EL1 - Processor Feature Register 0
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- let fp = bits_shift ( aa64pfr0, 19 , 16 ) < 0xF ;
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- let fphp = bits_shift ( aa64pfr0, 19 , 16 ) >= 1 ;
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- let asimd = bits_shift ( aa64pfr0, 23 , 20 ) < 0xF ;
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- let asimdhp = bits_shift ( aa64pfr0, 23 , 20 ) >= 1 ;
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- enable_feature ( Feature :: fp, fp) ;
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- enable_feature ( Feature :: fp16, fphp) ;
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- // SIMD support requires float support - if half-floats are
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- // supported, it also requires half-float support:
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- enable_feature ( Feature :: asimd, fp && asimd && ( !fphp | asimdhp) ) ;
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- // SIMD extensions require SIMD support:
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- enable_feature ( Feature :: aes, asimd && bits_shift ( aa64isar0, 7 , 4 ) >= 1 ) ;
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- let sha1 = bits_shift ( aa64isar0, 11 , 8 ) >= 1 ;
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- let sha2 = bits_shift ( aa64isar0, 15 , 12 ) >= 1 ;
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- enable_feature ( Feature :: sha2, asimd && sha1 && sha2) ;
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- enable_feature ( Feature :: rdm, asimd && bits_shift ( aa64isar0, 31 , 28 ) >= 1 ) ;
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- enable_feature (
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- Feature :: dotprod,
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- asimd && bits_shift ( aa64isar0, 47 , 44 ) >= 1 ,
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- ) ;
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- enable_feature ( Feature :: sve, asimd && bits_shift ( aa64pfr0, 35 , 32 ) >= 1 ) ;
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+ if let Some ( aa64pfr0) = aa64pfr0 {
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+ let fp = bits_shift ( aa64pfr0, 19 , 16 ) < 0xF ;
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+ let fphp = bits_shift ( aa64pfr0, 19 , 16 ) >= 1 ;
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+ let asimd = bits_shift ( aa64pfr0, 23 , 20 ) < 0xF ;
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+ let asimdhp = bits_shift ( aa64pfr0, 23 , 20 ) >= 1 ;
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+ enable_feature ( Feature :: fp, fp) ;
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+ enable_feature ( Feature :: fp16, fphp) ;
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+ // SIMD support requires float support - if half-floats are
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+ // supported, it also requires half-float support:
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+ enable_feature ( Feature :: asimd, fp && asimd && ( !fphp | asimdhp) ) ;
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+ // SIMD extensions require SIMD support:
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+ enable_feature ( Feature :: aes, asimd && bits_shift ( aa64isar0, 7 , 4 ) >= 1 ) ;
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+ let sha1 = bits_shift ( aa64isar0, 11 , 8 ) >= 1 ;
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+ let sha2 = bits_shift ( aa64isar0, 15 , 12 ) >= 1 ;
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+ enable_feature ( Feature :: sha2, asimd && sha1 && sha2) ;
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+ enable_feature ( Feature :: rdm, asimd && bits_shift ( aa64isar0, 31 , 28 ) >= 1 ) ;
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+ enable_feature (
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+ Feature :: dotprod,
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+ asimd && bits_shift ( aa64isar0, 47 , 44 ) >= 1 ,
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+ ) ;
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+ enable_feature ( Feature :: sve, asimd && bits_shift ( aa64pfr0, 35 , 32 ) >= 1 ) ;
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+ }
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// ID_AA64PFR0_EL1 - Processor Feature Register 0
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// Check for either APA or API field
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