WIP add vld1q_f32

The alignment requirements should match the pointer type. See
llvm commit 8beaba13b8a61697008854b82ed3b45377af9d9d

Author: jrmuizel

crates/core_arch/src/aarch64/neon/mod.rs

@@ -1799,6 +1799,13 @@ pub unsafe fn vqtbx4q_p8(a: poly8x16_t, t: poly8x16x4_t, idx: uint8x16_t) -> pol
     ))
 }
 
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(test, assert_instr(ldr))]
+pub unsafe fn vld1q_f32(addr: *const f32) -> float32x4_t {
+    transmute(f32x4::new(*addr, *addr.offset(1), *addr.offset(2), *addr.offset(3)))
+}
+
 #[cfg(test)]
 mod tests {
     use crate::core_arch::aarch64::test_support::*;
@@ -1807,6 +1814,14 @@ mod tests {
     use std::mem::transmute;
     use stdarch_test::simd_test;
 
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_f32() {
+        let a = f32x4::new(1., 2., 3., 4.);
+        let e = a;
+        let r: f32x4 = transmute(vld1q_f32(transmute(&a)));
+        assert_eq!(r, e);
+    }
+
     #[simd_test(enable = "neon")]
     unsafe fn test_vpaddq_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);

crates/core_arch/src/arm/neon/mod.rs

@@ -63,7 +63,7 @@ types! {
     /// ARM-specific 128-bit wide vector of four packed `u32`.
     pub struct uint32x4_t(u32, u32, u32, u32);
     /// ARM-specific 128-bit wide vector of four packed `f32`.
-    pub struct float32x4_t(f32, f32, f32, f32);
+    pub struct float32x4_t(pub f32, pub f32, pub f32, pub f32);
     /// ARM-specific 128-bit wide vector of two packed `i64`.
     pub struct int64x2_t(i64, i64);
     /// ARM-specific 128-bit wide vector of two packed `u64`.
@@ -217,6 +217,8 @@ extern "C" {
         d: int8x8_t,
         e: int8x8_t,
     ) -> int8x8_t;
+    #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32.p0i8")]
+    fn vld1q_v4f32(addr: *const u8, align: u32) -> float32x4_t;
 }
 
 /// Absolute value (wrapping).
@@ -1767,6 +1769,16 @@ pub unsafe fn vld1q_u8(addr: *const u8) -> uint8x16_t {
     ptr::read(addr as *const uint8x16_t)
 }
 
+/// Load multiple single-element structures to one, two, three, or four registers
+#[inline]
+#[cfg(target_arch = "arm")]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(test, assert_instr(ldr))]
+pub unsafe fn vld1q_f32(addr: *const f32) -> float32x4_t {
+    vld1q_v4f32(addr as *const u8, 4)
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;
@@ -1791,6 +1803,15 @@ mod tests {
         assert_eq!(r, e);
     }
 
+    #[cfg(target_arch = "arm")]
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vld1q_f32() {
+        let a = f32x4::new(1., 2., 3., 4.);
+        let e = a;
+        let r: f32x4 = transmute(vld1q_f32(transmute(&a)));
+        assert_eq!(r, e);
+    }
+
     #[simd_test(enable = "neon")]
     unsafe fn test_vget_lane_u8() {
         let v = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);