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Don't require AVX512 for 128/256-bit GFNI & VPCLMULQDQ intrinsics (#1349)
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3 files changed

+19
-13
lines changed

3 files changed

+19
-13
lines changed

crates/core_arch/src/x86/avx512gfni.rs

+9-9
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ pub unsafe fn _mm512_maskz_gf2p8mul_epi8(k: __mmask64, a: __m512i, b: __m512i) -
121121
///
122122
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8mul_epi8)
123123
#[inline]
124-
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
124+
#[target_feature(enable = "avx512gfni,avx")]
125125
#[cfg_attr(test, assert_instr(vgf2p8mulb))]
126126
pub unsafe fn _mm256_gf2p8mul_epi8(a: __m256i, b: __m256i) -> __m256i {
127127
transmute(vgf2p8mulb_256(a.as_i8x32(), b.as_i8x32()))
@@ -177,8 +177,8 @@ pub unsafe fn _mm256_maskz_gf2p8mul_epi8(k: __mmask32, a: __m256i, b: __m256i) -
177177
///
178178
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8mul_epi8)
179179
#[inline]
180-
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
181-
#[cfg_attr(test, assert_instr(vgf2p8mulb))]
180+
#[target_feature(enable = "avx512gfni")]
181+
#[cfg_attr(test, assert_instr(gf2p8mulb))]
182182
pub unsafe fn _mm_gf2p8mul_epi8(a: __m128i, b: __m128i) -> __m128i {
183183
transmute(vgf2p8mulb_128(a.as_i8x16(), b.as_i8x16()))
184184
}
@@ -307,7 +307,7 @@ pub unsafe fn _mm512_mask_gf2p8affine_epi64_epi8<const B: i32>(
307307
///
308308
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8affine_epi8)
309309
#[inline]
310-
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
310+
#[target_feature(enable = "avx512gfni,avx")]
311311
#[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))]
312312
#[rustc_legacy_const_generics(2)]
313313
pub unsafe fn _mm256_gf2p8affine_epi64_epi8<const B: i32>(x: __m256i, a: __m256i) -> __m256i {
@@ -380,8 +380,8 @@ pub unsafe fn _mm256_mask_gf2p8affine_epi64_epi8<const B: i32>(
380380
///
381381
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affine_epi8)
382382
#[inline]
383-
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
384-
#[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))]
383+
#[target_feature(enable = "avx512gfni")]
384+
#[cfg_attr(test, assert_instr(gf2p8affineqb, B = 0))]
385385
#[rustc_legacy_const_generics(2)]
386386
pub unsafe fn _mm_gf2p8affine_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) -> __m128i {
387387
static_assert_imm8!(B);
@@ -534,7 +534,7 @@ pub unsafe fn _mm512_mask_gf2p8affineinv_epi64_epi8<const B: i32>(
534534
///
535535
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8affineinv_epi64_epi8)
536536
#[inline]
537-
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
537+
#[target_feature(enable = "avx512gfni,avx")]
538538
#[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))]
539539
#[rustc_legacy_const_generics(2)]
540540
pub unsafe fn _mm256_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m256i, a: __m256i) -> __m256i {
@@ -613,8 +613,8 @@ pub unsafe fn _mm256_mask_gf2p8affineinv_epi64_epi8<const B: i32>(
613613
///
614614
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affineinv_epi64_epi8)
615615
#[inline]
616-
#[target_feature(enable = "avx512gfni,avx512bw,avx512vl")]
617-
#[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))]
616+
#[target_feature(enable = "avx512gfni")]
617+
#[cfg_attr(test, assert_instr(gf2p8affineinvqb, B = 0))]
618618
#[rustc_legacy_const_generics(2)]
619619
pub unsafe fn _mm_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) -> __m128i {
620620
static_assert_imm8!(B);

crates/core_arch/src/x86/avx512vpclmulqdq.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ pub unsafe fn _mm512_clmulepi64_epi128<const IMM8: i32>(a: __m512i, b: __m512i)
5050
///
5151
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_clmulepi64_epi128)
5252
#[inline]
53-
#[target_feature(enable = "avx512vpclmulqdq,avx512vl")]
53+
#[target_feature(enable = "avx512vpclmulqdq")]
5454
#[cfg_attr(test, assert_instr(vpclmul, IMM8 = 0))]
5555
#[rustc_legacy_const_generics(2)]
5656
pub unsafe fn _mm256_clmulepi64_epi128<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {

crates/stdarch-verify/tests/x86-intel.rs

+9-3
Original file line numberDiff line numberDiff line change
@@ -471,9 +471,15 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
471471
continue;
472472
}
473473

474-
// Some AMD CPUs support VAES without AVX512, even though the Intel
475-
// documentation states that those instructions require AVX512VL.
476-
if *cpuid == "AVX512VL" && intel.cpuid.contains(&"VAES".to_string()) {
474+
// Some CPUs support VAES/GFNI/VPCLMULQDQ without AVX512, even though
475+
// the Intel documentation states that those instructions require
476+
// AVX512VL.
477+
if *cpuid == "AVX512VL"
478+
&& intel
479+
.cpuid
480+
.iter()
481+
.any(|x| matches!(&**x, "VAES" | "GFNI" | "VPCLMULQDQ"))
482+
{
477483
continue;
478484
}
479485

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