Fix cancellation code arithmetic

Author: vertexclique

crates/core_arch/src/aarch64/tme.rs

@@ -1,18 +1,18 @@
 //! ARM's Transactional Memory Extensions (TME).
 //!
-//! This CPU feature is available on Aarch64 – ARMv8-A arch. onwards.
+//! This CPU feature is available on Aarch64 - A architecture profile.
 //! This feature is in the non-neon feature set. TME specific vendor documentation can
 //! be found [TME Intrinsics Introduction][tme_intrinsics_intro].
 //!
 //! The reference is [ACLE Q4 2019][acle_q4_2019_ref].
 //!
 //! ACLE has a section for TME extensions and state masks for aborts and failure codes.
-//! In addition to that [LLVM Aarch64 Intrinsics][llvm_aarch64_int] are
-//! self explanatory for what needs to be exported.
+//! [ARM A64 Architecture Register Datasheet][a_profile_future] also describes possible failure code scenarios.
 //!
 //! [acle_q4_2019_ref]: https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf
 //! [tme_intrinsics_intro]: https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics
 //! [llvm_aarch64_int]: https://github.com/llvm/llvm-project/commit/a36d31478c182903523e04eb271bbf102bfab2cc#diff-ff24e1c35f4d54f1110ce5d90c709319R626-R646
+//! [a_profile_future]: https://static.docs.arm.com/ddi0601/a/SysReg_xml_futureA-2019-04.pdf?_ga=2.116560387.441514988.1590524918-1110153136.1588469296
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
@@ -61,7 +61,7 @@ pub const _TMFAILURE_DBG: u32 = 1 << 22;
 ///
 pub const _TMFAILURE_INT: u32 = 1 << 23;
 
-///
+/// Transaction aborted in trivial TM implementation
 pub const _TMFAILURE_TRIVIAL: u32 = 1 << 24;
 
 
@@ -116,9 +116,72 @@ pub unsafe fn __ttest() -> u32 {
     aarch64_ttest() as _
 }
 
-/// Encodes cancellation reason, which is the parameter passed to [`__tcancel`]
-/// Takes cancellation reason flags and retry-ability.
-#[inline]
-pub const fn _tcancel_code(reason: u32, retryable: bool) -> u32 {
-    (retryable as i32) << 15 | (reason & _TMFAILURE_REASON)
+
+#[cfg(test)]
+mod tests {
+    use stdarch_test::simd_test;
+
+    use crate::core_arch::aarch64::*;
+
+    #[simd_test(enable = "tme")]
+    unsafe fn test_tstart() {
+        let mut x = 0;
+        for i in 0..10 {
+            let code = tme::__tstart();
+            if code == _TMSTART_SUCCESS {
+                x += 1;
+                assert_eq!(x, i+1);
+                break;
+            }
+            assert_eq!(x, 0);
+        }
+    }
+
+    #[simd_test(enable = "tme")]
+    unsafe fn test_tcommit() {
+        let mut x = 0;
+        for i in 0..10 {
+            let code = tme::__tstart();
+            if code == _TMSTART_SUCCESS {
+                x += 1;
+                assert_eq!(x, i+1);
+                tme::__tcommit();
+            }
+            assert_eq!(x, i+1);
+        }
+    }
+
+    #[simd_test(enable = "tme")]
+    unsafe fn test_tcancel() {
+        let reason = 0x123;
+        let cancel_code = (0 | (reason & _TMFAILURE_REASON) as i32) as u32;
+        let mut x = 0;
+
+        for i in 0..10 {
+            let code = tme::__tstart();
+            if code == _TMSTART_SUCCESS {
+                x += 1;
+                assert_eq!(x, i+1);
+                tme::__tcancel(cancel_code);
+                break;
+            }
+        }
+
+        assert_eq!(x, 0);
+    }
+
+    #[simd_test(enable = "tme")]
+    unsafe fn test_ttest() {
+        let reason = 0x123;
+        let cancel_code = (0 | (reason & _TMFAILURE_REASON) as i32) as u32;
+        for _ in 0..10 {
+            let code = tme::__tstart();
+            if code == _TMSTART_SUCCESS {
+                if tme::__ttest() == 2 {
+              	     tme::__tcancel(cancel_code);
+                  	 break;
+                }
+            }
+        }
+    }
 }

crates/stdarch-verify/tests/arm.rs

@@ -366,6 +366,7 @@ fn verify_all_signatures() {
                     && !rust.file.ends_with("v6.rs\"")
                     && !rust.file.ends_with("v7.rs\"")
                     && !rust.file.ends_with("v8.rs\"")
+                    && !rust.file.ends_with("tme.rs\"")
                 {
                     println!(
                         "missing arm definition for {:?} in {}",