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[doc] document all missing items
1 parent 7b7822f commit 87537ef

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+161
-81
lines changed

‎.appveyor.yml

+2-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,8 @@ install:
1919
build: false
2020

2121
test_script:
22-
- C:\msys64\usr\bin\sh ci\run.sh
22+
- cargo test --target %TARGET%
23+
- cargo test --target %TARGET% --release
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branches:
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only:

‎src/lib.rs

+1-1
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@@ -124,7 +124,7 @@
124124
#![cfg_attr(test, feature(proc_macro, test))]
125125

126126
#![cfg_attr(feature = "cargo-clippy",
127-
allow(inline_always, too_many_arguments, missing_docs_in_private_items,
127+
allow(inline_always, too_many_arguments,
128128
cast_sign_loss, cast_lossless, cast_possible_wrap,
129129
cast_possible_truncation, cast_precision_loss, shadow_reuse,
130130
cyclomatic_complexity, similar_names

‎src/macros.rs

+2
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@@ -1,3 +1,5 @@
1+
//! Utility macros
2+
13
macro_rules! define_ty {
24
($name:ident, $($elty:ident),+) => {
35
#[repr(simd)]

‎src/simd_llvm.rs

+4
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@@ -1,3 +1,7 @@
1+
//! LLVM's simd platform intrinsics
2+
//!
3+
//! TODO: should use `link_llvm_intrinsic` instead: issue #112
4+
15
extern "platform-intrinsic" {
26
pub fn simd_eq<T, U>(x: T, y: T) -> U;
37
pub fn simd_ne<T, U>(x: T, y: T) -> U;

‎src/v128.rs

+2
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@@ -1,3 +1,5 @@
1+
//! 128-bit wide vector types
2+
13
use simd_llvm::*;
24

35
define_ty! { f64x2, f64, f64 }

‎src/v256.rs

+2
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@@ -1,3 +1,5 @@
1+
//! 256-bit wide vector types
2+
13
use simd_llvm::*;
24

35
define_ty! { f64x4, f64, f64, f64, f64 }

‎src/v512.rs

+2
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
//! 512-bit wide vector types
2+
13
use simd_llvm::*;
24

35
define_ty! { f64x8, f64, f64, f64, f64, f64, f64, f64, f64 }

‎src/v64.rs

+2
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
//! 64-bit wide vector types
2+
13
use simd_llvm::*;
24

35
define_ty_doc! {

‎src/x86/avx.rs

+44-33
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,12 @@
1+
//! Advanced Vector Extensions (AVX)
2+
//!
3+
//! The references are:
4+
//!
5+
//! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2: Instruction Set Reference, A-Z](http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf).
6+
//! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions](http://support.amd.com/TechDocs/24594.pdf).
7+
//!
8+
//! [Wikipedia](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions) provides a quick overview of the instructions available.
9+
110
use std::mem;
211
use std::ptr;
312

@@ -494,69 +503,69 @@ pub unsafe fn _mm256_xor_ps(a: f32x8, b: f32x8) -> f32x8 {
494503
mem::transmute(a ^ b)
495504
}
496505

497-
// Equal (ordered, non-signaling)
506+
/// Equal (ordered, non-signaling)
498507
pub const _CMP_EQ_OQ: u8 = 0x00;
499-
// Less-than (ordered, signaling)
508+
/// Less-than (ordered, signaling)
500509
pub const _CMP_LT_OS: u8 = 0x01;
501-
// Less-than-or-equal (ordered, signaling)
510+
/// Less-than-or-equal (ordered, signaling)
502511
pub const _CMP_LE_OS: u8 = 0x02;
503-
// Unordered (non-signaling)
512+
/// Unordered (non-signaling)
504513
pub const _CMP_UNORD_Q: u8 = 0x03;
505-
// Not-equal (unordered, non-signaling)
514+
/// Not-equal (unordered, non-signaling)
506515
pub const _CMP_NEQ_UQ: u8 = 0x04;
507-
// Not-less-than (unordered, signaling)
516+
/// Not-less-than (unordered, signaling)
508517
pub const _CMP_NLT_US: u8 = 0x05;
509-
// Not-less-than-or-equal (unordered, signaling)
518+
/// Not-less-than-or-equal (unordered, signaling)
510519
pub const _CMP_NLE_US: u8 = 0x06;
511-
// Ordered (non-signaling)
520+
/// Ordered (non-signaling)
512521
pub const _CMP_ORD_Q: u8 = 0x07;
513-
// Equal (unordered, non-signaling)
522+
/// Equal (unordered, non-signaling)
514523
pub const _CMP_EQ_UQ: u8 = 0x08;
515-
// Not-greater-than-or-equal (unordered, signaling)
524+
/// Not-greater-than-or-equal (unordered, signaling)
516525
pub const _CMP_NGE_US: u8 = 0x09;
517-
// Not-greater-than (unordered, signaling)
526+
/// Not-greater-than (unordered, signaling)
518527
pub const _CMP_NGT_US: u8 = 0x0a;
519-
// False (ordered, non-signaling)
528+
/// False (ordered, non-signaling)
520529
pub const _CMP_FALSE_OQ: u8 = 0x0b;
521-
// Not-equal (ordered, non-signaling)
530+
/// Not-equal (ordered, non-signaling)
522531
pub const _CMP_NEQ_OQ: u8 = 0x0c;
523-
// Greater-than-or-equal (ordered, signaling)
532+
/// Greater-than-or-equal (ordered, signaling)
524533
pub const _CMP_GE_OS: u8 = 0x0d;
525-
// Greater-than (ordered, signaling)
534+
/// Greater-than (ordered, signaling)
526535
pub const _CMP_GT_OS: u8 = 0x0e;
527-
// True (unordered, non-signaling)
536+
/// True (unordered, non-signaling)
528537
pub const _CMP_TRUE_UQ: u8 = 0x0f;
529-
// Equal (ordered, signaling)
538+
/// Equal (ordered, signaling)
530539
pub const _CMP_EQ_OS: u8 = 0x10;
531-
// Less-than (ordered, non-signaling)
540+
/// Less-than (ordered, non-signaling)
532541
pub const _CMP_LT_OQ: u8 = 0x11;
533-
// Less-than-or-equal (ordered, non-signaling)
542+
/// Less-than-or-equal (ordered, non-signaling)
534543
pub const _CMP_LE_OQ: u8 = 0x12;
535-
// Unordered (signaling)
544+
/// Unordered (signaling)
536545
pub const _CMP_UNORD_S: u8 = 0x13;
537-
// Not-equal (unordered, signaling)
546+
/// Not-equal (unordered, signaling)
538547
pub const _CMP_NEQ_US: u8 = 0x14;
539-
// Not-less-than (unordered, non-signaling)
548+
/// Not-less-than (unordered, non-signaling)
540549
pub const _CMP_NLT_UQ: u8 = 0x15;
541-
// Not-less-than-or-equal (unordered, non-signaling)
550+
/// Not-less-than-or-equal (unordered, non-signaling)
542551
pub const _CMP_NLE_UQ: u8 = 0x16;
543-
// Ordered (signaling)
552+
/// Ordered (signaling)
544553
pub const _CMP_ORD_S: u8 = 0x17;
545-
// Equal (unordered, signaling)
554+
/// Equal (unordered, signaling)
546555
pub const _CMP_EQ_US: u8 = 0x18;
547-
// Not-greater-than-or-equal (unordered, non-signaling)
556+
/// Not-greater-than-or-equal (unordered, non-signaling)
548557
pub const _CMP_NGE_UQ: u8 = 0x19;
549-
// Not-greater-than (unordered, non-signaling)
558+
/// Not-greater-than (unordered, non-signaling)
550559
pub const _CMP_NGT_UQ: u8 = 0x1a;
551-
// False (ordered, signaling)
560+
/// False (ordered, signaling)
552561
pub const _CMP_FALSE_OS: u8 = 0x1b;
553-
// Not-equal (ordered, signaling)
562+
/// Not-equal (ordered, signaling)
554563
pub const _CMP_NEQ_OS: u8 = 0x1c;
555-
// Greater-than-or-equal (ordered, non-signaling)
564+
/// Greater-than-or-equal (ordered, non-signaling)
556565
pub const _CMP_GE_OQ: u8 = 0x1d;
557-
// Greater-than (ordered, non-signaling)
566+
/// Greater-than (ordered, non-signaling)
558567
pub const _CMP_GT_OQ: u8 = 0x1e;
559-
// True (unordered, signaling)
568+
/// True (unordered, signaling)
560569
pub const _CMP_TRUE_US: u8 = 0x1f;
561570

562571
/// Compare packed double-precision (64-bit) floating-point
@@ -826,7 +835,7 @@ pub unsafe fn _mm256_permute_ps(a: f32x8, imm8: i32) -> f32x8 {
826835
macro_rules! shuffle4 {
827836
($a:expr, $b:expr, $c:expr, $d:expr) => {
828837
simd_shuffle8(a, _mm256_undefined_ps(), [
829-
$a, $b, $c, $d, add4($a), add4($b), add4($c), add4($d)
838+
$a, $b, $c, $d, $a + 4, $b + 4, $c + 4, $d + 4
830839
])
831840
}
832841
}
@@ -922,6 +931,8 @@ pub unsafe fn _mm_permute_ps(a: f32x4, imm8: i32) -> f32x4 {
922931
}
923932
}
924933

934+
/// Shuffle double-precision (64-bit) floating-point elements in `a`
935+
/// within 256-bit lanes using the control in `b`.
925936
#[inline(always)]
926937
#[target_feature = "+avx"]
927938
#[cfg_attr(test, assert_instr(vpermilpd))]

‎src/x86/avx2.rs

+37-16
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,27 @@
1+
//! Advanced Vector Extensions 2 (AVX)
2+
//!
3+
//! AVX2 expands most AVX commands to 256-bit wide vector registers and
4+
//! adds [FMA](https://en.wikipedia.org/wiki/Fused_multiply-accumulate).
5+
//!
6+
//! The references are:
7+
//!
8+
//! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
9+
//! Instruction Set Reference, A-Z][intel64_ref].
10+
//! - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
11+
//! System Instructions][amd64_ref].
12+
//!
13+
//! Wikipedia's [AVX][wiki_avx] and [FMA][wiki_fma] pages provide a quick
14+
//! overview of the instructions available.
15+
//!
16+
//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
17+
//! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
18+
//! [wiki_avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
19+
//! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
20+
121
use simd_llvm::simd_cast;
222
use simd_llvm::{simd_shuffle2, simd_shuffle4, simd_shuffle8};
323
use simd_llvm::{simd_shuffle16, simd_shuffle32};
24+
425
use v256::*;
526
use v128::*;
627
use x86::__m256i;
@@ -122,22 +143,22 @@ pub unsafe fn _mm256_alignr_epi8(a: i8x32, b: i8x32, n: i32) -> i8x32 {
122143
macro_rules! shuffle {
123144
($shift:expr) => {
124145
simd_shuffle32(b, a, [
125-
add(0, $shift), add(1, $shift),
126-
add(2, $shift), add(3, $shift),
127-
add(4, $shift), add(5, $shift),
128-
add(6, $shift), add(7, $shift),
129-
add(8, $shift), add(9, $shift),
130-
add(10, $shift), add(11, $shift),
131-
add(12, $shift), add(13, $shift),
132-
add(14, $shift), add(15, $shift),
133-
add(16, $shift), add(17, $shift),
134-
add(18, $shift), add(19, $shift),
135-
add(20, $shift), add(21, $shift),
136-
add(22, $shift), add(23, $shift),
137-
add(24, $shift), add(25, $shift),
138-
add(26, $shift), add(27, $shift),
139-
add(28, $shift), add(29, $shift),
140-
add(30, $shift), add(31, $shift),
146+
0 + $shift, 1 + $shift,
147+
2 + $shift, 3 + $shift,
148+
4 + $shift, 5 + $shift,
149+
6 + $shift, 7 + $shift,
150+
8 + $shift, 9 + $shift,
151+
10 + $shift, 11 + $shift,
152+
12 + $shift, 13 + $shift,
153+
14 + $shift, 15 + $shift,
154+
16 + $shift, 17 + $shift,
155+
18 + $shift, 19 + $shift,
156+
20 + $shift, 21 + $shift,
157+
22 + $shift, 23 + $shift,
158+
24 + $shift, 25 + $shift,
159+
26 + $shift, 27 + $shift,
160+
28 + $shift, 29 + $shift,
161+
30 + $shift, 31 + $shift,
141162
])
142163
}
143164
}

‎src/x86/macros.rs

+2
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
//! Utility macros.
2+
13
macro_rules! constify_imm8 {
24
($imm8:expr, $expand:ident) => {
35
#[allow(overflowing_literals)]

‎src/x86/mod.rs

+4
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
//! x86 intrinsics
2+
13
pub use self::sse::*;
24
pub use self::sse2::*;
35
pub use self::sse3::*;
@@ -14,8 +16,10 @@ pub use self::tbm::*;
1416

1517
pub use self::runtime::{__unstable_detect_feature, __Feature};
1618

19+
/// 128-bit wide signed integer vector type
1720
#[allow(non_camel_case_types)]
1821
pub type __m128i = ::v128::i8x16;
22+
/// 256-bit wide signed integer vector type
1923
#[allow(non_camel_case_types)]
2024
pub type __m256i = ::v256::i8x32;
2125

‎src/x86/sse.rs

+15
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
//! Streaming SIMD Extensions (SSE)
2+
13
use simd_llvm::simd_shuffle4;
24
use v128::*;
35
use v64::f32x2;
@@ -1455,6 +1457,7 @@ pub const _MM_EXCEPT_OVERFLOW: u32 = 0x0008;
14551457
pub const _MM_EXCEPT_UNDERFLOW: u32 = 0x0010;
14561458
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14571459
pub const _MM_EXCEPT_INEXACT: u32 = 0x0020;
1460+
/// See [`_MM_GET_EXCEPTION_STATE`](fn._MM_GET_EXCEPTION_STATE.html)
14581461
pub const _MM_EXCEPT_MASK: u32 = 0x003f;
14591462

14601463
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
@@ -1469,6 +1472,7 @@ pub const _MM_MASK_OVERFLOW: u32 = 0x0400;
14691472
pub const _MM_MASK_UNDERFLOW: u32 = 0x0800;
14701473
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14711474
pub const _MM_MASK_INEXACT: u32 = 0x1000;
1475+
/// See [`_MM_GET_EXCEPTION_MASK`](fn._MM_GET_EXCEPTION_MASK.html)
14721476
pub const _MM_MASK_MASK: u32 = 0x1f80;
14731477

14741478
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
@@ -1479,56 +1483,66 @@ pub const _MM_ROUND_DOWN: u32 = 0x2000;
14791483
pub const _MM_ROUND_UP: u32 = 0x4000;
14801484
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14811485
pub const _MM_ROUND_TOWARD_ZERO: u32 = 0x6000;
1486+
1487+
/// See [`_MM_GET_ROUNDING_MODE`](fn._MM_GET_ROUNDING_MODE.html)
14821488
pub const _MM_ROUND_MASK: u32 = 0x6000;
14831489

1490+
/// See [`_MM_GET_FLUSH_ZERO_MODE`](fn._MM_GET_FLUSH_ZERO_MODE.html)
14841491
pub const _MM_FLUSH_ZERO_MASK: u32 = 0x8000;
14851492
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14861493
pub const _MM_FLUSH_ZERO_ON: u32 = 0x8000;
14871494
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14881495
pub const _MM_FLUSH_ZERO_OFF: u32 = 0x0000;
14891496

1497+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14901498
#[inline(always)]
14911499
#[allow(non_snake_case)]
14921500
#[target_feature = "+sse"]
14931501
pub unsafe fn _MM_GET_EXCEPTION_MASK() -> u32 {
14941502
_mm_getcsr() & _MM_MASK_MASK
14951503
}
14961504

1505+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
14971506
#[inline(always)]
14981507
#[allow(non_snake_case)]
14991508
#[target_feature = "+sse"]
15001509
pub unsafe fn _MM_GET_EXCEPTION_STATE() -> u32 {
15011510
_mm_getcsr() & _MM_EXCEPT_MASK
15021511
}
15031512

1513+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
15041514
#[inline(always)]
15051515
#[allow(non_snake_case)]
15061516
#[target_feature = "+sse"]
15071517
pub unsafe fn _MM_GET_FLUSH_ZERO_MODE() -> u32 {
15081518
_mm_getcsr() & _MM_FLUSH_ZERO_MASK
15091519
}
15101520

1521+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
15111522
#[inline(always)]
15121523
#[allow(non_snake_case)]
15131524
#[target_feature = "+sse"]
15141525
pub unsafe fn _MM_GET_ROUNDING_MODE() -> u32 {
15151526
_mm_getcsr() & _MM_ROUND_MASK
15161527
}
15171528

1529+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
15181530
#[inline(always)]
15191531
#[allow(non_snake_case)]
15201532
#[target_feature = "+sse"]
15211533
pub unsafe fn _MM_SET_EXCEPTION_MASK(x: u32) {
15221534
_mm_setcsr((_mm_getcsr() & !_MM_MASK_MASK) | x)
15231535
}
15241536

1537+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
15251538
#[inline(always)]
15261539
#[allow(non_snake_case)]
15271540
#[target_feature = "+sse"]
15281541
pub unsafe fn _MM_SET_EXCEPTION_STATE(x: u32) {
15291542
_mm_setcsr((_mm_getcsr() & !_MM_EXCEPT_MASK) | x)
15301543
}
15311544

1545+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
15321546
#[inline(always)]
15331547
#[allow(non_snake_case)]
15341548
#[target_feature = "+sse"]
@@ -1538,6 +1552,7 @@ pub unsafe fn _MM_SET_FLUSH_ZERO_MODE(x: u32) {
15381552
_mm_setcsr(val)
15391553
}
15401554

1555+
/// See [`_mm_setcsr`](fn._mm_setcsr.html)
15411556
#[inline(always)]
15421557
#[allow(non_snake_case)]
15431558
#[target_feature = "+sse"]

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