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add vshl and vshr neon instructions (#1111)
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+4917
-3275
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5 files changed

+4917
-3275
lines changed

crates/core_arch/src/aarch64/neon/generated.rs

+228
Original file line numberDiff line numberDiff line change
@@ -3640,6 +3640,132 @@ pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
36403640
transmute(a)
36413641
}
36423642

3643+
/// Signed shift left long
3644+
#[inline]
3645+
#[target_feature(enable = "neon")]
3646+
#[cfg_attr(test, assert_instr(sshll2, N = 2))]
3647+
#[rustc_legacy_const_generics(1)]
3648+
pub unsafe fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
3649+
static_assert!(N : i32 where N >= 0 && N <= 8);
3650+
let b: int8x8_t = simd_shuffle8(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
3651+
vshll_n_s8::<N>(b)
3652+
}
3653+
3654+
/// Signed shift left long
3655+
#[inline]
3656+
#[target_feature(enable = "neon")]
3657+
#[cfg_attr(test, assert_instr(sshll2, N = 2))]
3658+
#[rustc_legacy_const_generics(1)]
3659+
pub unsafe fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
3660+
static_assert!(N : i32 where N >= 0 && N <= 16);
3661+
let b: int16x4_t = simd_shuffle4(a, a, [4, 5, 6, 7]);
3662+
vshll_n_s16::<N>(b)
3663+
}
3664+
3665+
/// Signed shift left long
3666+
#[inline]
3667+
#[target_feature(enable = "neon")]
3668+
#[cfg_attr(test, assert_instr(sshll2, N = 2))]
3669+
#[rustc_legacy_const_generics(1)]
3670+
pub unsafe fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
3671+
static_assert!(N : i32 where N >= 0 && N <= 32);
3672+
let b: int32x2_t = simd_shuffle2(a, a, [2, 3]);
3673+
vshll_n_s32::<N>(b)
3674+
}
3675+
3676+
/// Signed shift left long
3677+
#[inline]
3678+
#[target_feature(enable = "neon")]
3679+
#[cfg_attr(test, assert_instr(ushll2, N = 2))]
3680+
#[rustc_legacy_const_generics(1)]
3681+
pub unsafe fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
3682+
static_assert!(N : i32 where N >= 0 && N <= 8);
3683+
let b: uint8x8_t = simd_shuffle8(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
3684+
vshll_n_u8::<N>(b)
3685+
}
3686+
3687+
/// Signed shift left long
3688+
#[inline]
3689+
#[target_feature(enable = "neon")]
3690+
#[cfg_attr(test, assert_instr(ushll2, N = 2))]
3691+
#[rustc_legacy_const_generics(1)]
3692+
pub unsafe fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
3693+
static_assert!(N : i32 where N >= 0 && N <= 16);
3694+
let b: uint16x4_t = simd_shuffle4(a, a, [4, 5, 6, 7]);
3695+
vshll_n_u16::<N>(b)
3696+
}
3697+
3698+
/// Signed shift left long
3699+
#[inline]
3700+
#[target_feature(enable = "neon")]
3701+
#[cfg_attr(test, assert_instr(ushll2, N = 2))]
3702+
#[rustc_legacy_const_generics(1)]
3703+
pub unsafe fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
3704+
static_assert!(N : i32 where N >= 0 && N <= 32);
3705+
let b: uint32x2_t = simd_shuffle2(a, a, [2, 3]);
3706+
vshll_n_u32::<N>(b)
3707+
}
3708+
3709+
/// Shift right narrow
3710+
#[inline]
3711+
#[target_feature(enable = "neon")]
3712+
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
3713+
#[rustc_legacy_const_generics(2)]
3714+
pub unsafe fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
3715+
static_assert!(N : i32 where N >= 1 && N <= 8);
3716+
simd_shuffle16(a, vshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
3717+
}
3718+
3719+
/// Shift right narrow
3720+
#[inline]
3721+
#[target_feature(enable = "neon")]
3722+
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
3723+
#[rustc_legacy_const_generics(2)]
3724+
pub unsafe fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
3725+
static_assert!(N : i32 where N >= 1 && N <= 16);
3726+
simd_shuffle8(a, vshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7])
3727+
}
3728+
3729+
/// Shift right narrow
3730+
#[inline]
3731+
#[target_feature(enable = "neon")]
3732+
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
3733+
#[rustc_legacy_const_generics(2)]
3734+
pub unsafe fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
3735+
static_assert!(N : i32 where N >= 1 && N <= 32);
3736+
simd_shuffle4(a, vshrn_n_s64::<N>(b), [0, 1, 2, 3])
3737+
}
3738+
3739+
/// Shift right narrow
3740+
#[inline]
3741+
#[target_feature(enable = "neon")]
3742+
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
3743+
#[rustc_legacy_const_generics(2)]
3744+
pub unsafe fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
3745+
static_assert!(N : i32 where N >= 1 && N <= 8);
3746+
simd_shuffle16(a, vshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
3747+
}
3748+
3749+
/// Shift right narrow
3750+
#[inline]
3751+
#[target_feature(enable = "neon")]
3752+
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
3753+
#[rustc_legacy_const_generics(2)]
3754+
pub unsafe fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
3755+
static_assert!(N : i32 where N >= 1 && N <= 16);
3756+
simd_shuffle8(a, vshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7])
3757+
}
3758+
3759+
/// Shift right narrow
3760+
#[inline]
3761+
#[target_feature(enable = "neon")]
3762+
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
3763+
#[rustc_legacy_const_generics(2)]
3764+
pub unsafe fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
3765+
static_assert!(N : i32 where N >= 1 && N <= 32);
3766+
simd_shuffle4(a, vshrn_n_u64::<N>(b), [0, 1, 2, 3])
3767+
}
3768+
36433769
/// Transpose vectors
36443770
#[inline]
36453771
#[target_feature(enable = "neon")]
@@ -7619,6 +7745,108 @@ mod test {
76197745
assert_eq!(r, e);
76207746
}
76217747

7748+
#[simd_test(enable = "neon")]
7749+
unsafe fn test_vshll_high_n_s8() {
7750+
let a: i8x16 = i8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8);
7751+
let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32);
7752+
let r: i16x8 = transmute(vshll_high_n_s8::<2>(transmute(a)));
7753+
assert_eq!(r, e);
7754+
}
7755+
7756+
#[simd_test(enable = "neon")]
7757+
unsafe fn test_vshll_high_n_s16() {
7758+
let a: i16x8 = i16x8::new(0, 0, 1, 2, 1, 2, 3, 4);
7759+
let e: i32x4 = i32x4::new(4, 8, 12, 16);
7760+
let r: i32x4 = transmute(vshll_high_n_s16::<2>(transmute(a)));
7761+
assert_eq!(r, e);
7762+
}
7763+
7764+
#[simd_test(enable = "neon")]
7765+
unsafe fn test_vshll_high_n_s32() {
7766+
let a: i32x4 = i32x4::new(0, 0, 1, 2);
7767+
let e: i64x2 = i64x2::new(4, 8);
7768+
let r: i64x2 = transmute(vshll_high_n_s32::<2>(transmute(a)));
7769+
assert_eq!(r, e);
7770+
}
7771+
7772+
#[simd_test(enable = "neon")]
7773+
unsafe fn test_vshll_high_n_u8() {
7774+
let a: u8x16 = u8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8);
7775+
let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32);
7776+
let r: u16x8 = transmute(vshll_high_n_u8::<2>(transmute(a)));
7777+
assert_eq!(r, e);
7778+
}
7779+
7780+
#[simd_test(enable = "neon")]
7781+
unsafe fn test_vshll_high_n_u16() {
7782+
let a: u16x8 = u16x8::new(0, 0, 1, 2, 1, 2, 3, 4);
7783+
let e: u32x4 = u32x4::new(4, 8, 12, 16);
7784+
let r: u32x4 = transmute(vshll_high_n_u16::<2>(transmute(a)));
7785+
assert_eq!(r, e);
7786+
}
7787+
7788+
#[simd_test(enable = "neon")]
7789+
unsafe fn test_vshll_high_n_u32() {
7790+
let a: u32x4 = u32x4::new(0, 0, 1, 2);
7791+
let e: u64x2 = u64x2::new(4, 8);
7792+
let r: u64x2 = transmute(vshll_high_n_u32::<2>(transmute(a)));
7793+
assert_eq!(r, e);
7794+
}
7795+
7796+
#[simd_test(enable = "neon")]
7797+
unsafe fn test_vshrn_high_n_s16() {
7798+
let a: i8x8 = i8x8::new(1, 2, 5, 6, 5, 6, 7, 8);
7799+
let b: i16x8 = i16x8::new(20, 24, 28, 32, 52, 56, 60, 64);
7800+
let e: i8x16 = i8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16);
7801+
let r: i8x16 = transmute(vshrn_high_n_s16::<2>(transmute(a), transmute(b)));
7802+
assert_eq!(r, e);
7803+
}
7804+
7805+
#[simd_test(enable = "neon")]
7806+
unsafe fn test_vshrn_high_n_s32() {
7807+
let a: i16x4 = i16x4::new(1, 2, 5, 6);
7808+
let b: i32x4 = i32x4::new(20, 24, 28, 32);
7809+
let e: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8);
7810+
let r: i16x8 = transmute(vshrn_high_n_s32::<2>(transmute(a), transmute(b)));
7811+
assert_eq!(r, e);
7812+
}
7813+
7814+
#[simd_test(enable = "neon")]
7815+
unsafe fn test_vshrn_high_n_s64() {
7816+
let a: i32x2 = i32x2::new(1, 2);
7817+
let b: i64x2 = i64x2::new(20, 24);
7818+
let e: i32x4 = i32x4::new(1, 2, 5, 6);
7819+
let r: i32x4 = transmute(vshrn_high_n_s64::<2>(transmute(a), transmute(b)));
7820+
assert_eq!(r, e);
7821+
}
7822+
7823+
#[simd_test(enable = "neon")]
7824+
unsafe fn test_vshrn_high_n_u16() {
7825+
let a: u8x8 = u8x8::new(1, 2, 5, 6, 5, 6, 7, 8);
7826+
let b: u16x8 = u16x8::new(20, 24, 28, 32, 52, 56, 60, 64);
7827+
let e: u8x16 = u8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16);
7828+
let r: u8x16 = transmute(vshrn_high_n_u16::<2>(transmute(a), transmute(b)));
7829+
assert_eq!(r, e);
7830+
}
7831+
7832+
#[simd_test(enable = "neon")]
7833+
unsafe fn test_vshrn_high_n_u32() {
7834+
let a: u16x4 = u16x4::new(1, 2, 5, 6);
7835+
let b: u32x4 = u32x4::new(20, 24, 28, 32);
7836+
let e: u16x8 = u16x8::new(1, 2, 5, 6, 5, 6, 7, 8);
7837+
let r: u16x8 = transmute(vshrn_high_n_u32::<2>(transmute(a), transmute(b)));
7838+
assert_eq!(r, e);
7839+
}
7840+
7841+
#[simd_test(enable = "neon")]
7842+
unsafe fn test_vshrn_high_n_u64() {
7843+
let a: u32x2 = u32x2::new(1, 2);
7844+
let b: u64x2 = u64x2::new(20, 24);
7845+
let e: u32x4 = u32x4::new(1, 2, 5, 6);
7846+
let r: u32x4 = transmute(vshrn_high_n_u64::<2>(transmute(a), transmute(b)));
7847+
assert_eq!(r, e);
7848+
}
7849+
76227850
#[simd_test(enable = "neon")]
76237851
unsafe fn test_vtrn1_s8() {
76247852
let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14);

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